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hw/riscv: microchip_pfsoc: Map the reserved memory at address 0

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Somehow HSS needs to access address 0 [1] for the DDR calibration data
which is in the chipset's reserved memory. Let's map it.

[1] See the config_copy() calls in various places in ddr_setup() in
    the HSS source codes.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-9-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Bin Meng 2020-10-28 13:30:08 +08:00 committed by Alistair Francis
parent cdd58c70fb
commit 27c22b2de0
2 changed files with 11 additions and 1 deletions
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11
hw/riscv/microchip_pfsoc.c
View File

@ -90,7 +90,8 @@ static const struct MemmapEntry {
hwaddr base; hwaddr base;
hwaddr size; hwaddr size;
} microchip_pfsoc_memmap[] = { } microchip_pfsoc_memmap[] = {
[MICROCHIP_PFSOC_DEBUG] = { 0x0, 0x1000 }, [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 },
[MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 },
[MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 }, [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 },
[MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 }, [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 },
[MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 }, [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 },
@ -176,6 +177,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev); MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev);
const struct MemmapEntry *memmap = microchip_pfsoc_memmap; const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
MemoryRegion *system_memory = get_system_memory(); MemoryRegion *system_memory = get_system_memory();
MemoryRegion *rsvd0_mem = g_new(MemoryRegion, 1);
MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1); MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
MemoryRegion *envm_data = g_new(MemoryRegion, 1); MemoryRegion *envm_data = g_new(MemoryRegion, 1);
@ -195,6 +197,13 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
/* Reserved Memory at address 0 */
memory_region_init_ram(rsvd0_mem, NULL, "microchip.pfsoc.rsvd0_mem",
memmap[MICROCHIP_PFSOC_RSVD0].size, &error_fatal);
memory_region_add_subregion(system_memory,
memmap[MICROCHIP_PFSOC_RSVD0].base,
rsvd0_mem);
/* E51 DTIM */ /* E51 DTIM */
memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem", memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem",
memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal); memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal);

1
include/hw/riscv/microchip_pfsoc.h
View File

@ -74,6 +74,7 @@ typedef struct MicrochipIcicleKitState {
TYPE_MICROCHIP_ICICLE_KIT_MACHINE) TYPE_MICROCHIP_ICICLE_KIT_MACHINE)
enum { enum {
MICROCHIP_PFSOC_RSVD0,
MICROCHIP_PFSOC_DEBUG, MICROCHIP_PFSOC_DEBUG,
MICROCHIP_PFSOC_E51_DTIM, MICROCHIP_PFSOC_E51_DTIM,
MICROCHIP_PFSOC_BUSERR_UNIT0, MICROCHIP_PFSOC_BUSERR_UNIT0,