target/rx: CPU definitions
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> [PMD: Use newer QOM style, split cpu-qom.h, restrict access to extable array, use rx_cpu_tlb_fill() extracted from patch of Yoshinori Sato 'Convert to CPUClass::tlb_fill', call cpu_reset after qemu_init_vcpu, make rx_crname a function] Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20200224141923.82118-7-ysato@users.sourceforge.jp> Acked-by: Richard Henderson <richard.henderson@linaro.org> [PMD: Use GByteArray in gdbstub (rebase commita010bdbe), use device_class_set_parent_reset (rebase commit781c67ca)] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Yoshinori Sato
Philippe Mathieu-Daudé
parent
075d047e2b
commit
27a4a30e29
70
gdb-xml/rx-core.xml
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70
gdb-xml/rx-core.xml
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@ -0,0 +1,70 @@
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<?xml version="1.0"?>
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<!-- Copyright (C) 2019 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved. -->
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<!DOCTYPE feature SYSTEM "gdb-target.dtd">
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<feature name="org.gnu.gdb.rx.core">
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<reg name="r0" bitsize="32" type="data_ptr"/>
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<reg name="r1" bitsize="32" type="uint32"/>
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<reg name="r2" bitsize="32" type="uint32"/>
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<reg name="r3" bitsize="32" type="uint32"/>
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<reg name="r4" bitsize="32" type="uint32"/>
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<reg name="r5" bitsize="32" type="uint32"/>
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<reg name="r6" bitsize="32" type="uint32"/>
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<reg name="r7" bitsize="32" type="uint32"/>
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<reg name="r8" bitsize="32" type="uint32"/>
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<reg name="r9" bitsize="32" type="uint32"/>
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<reg name="r10" bitsize="32" type="uint32"/>
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<reg name="r11" bitsize="32" type="uint32"/>
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<reg name="r12" bitsize="32" type="uint32"/>
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<reg name="r13" bitsize="32" type="uint32"/>
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<reg name="r14" bitsize="32" type="uint32"/>
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<reg name="r15" bitsize="32" type="uint32"/>
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<flags id="psw_flags" size="4">
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<field name="C" start="0" end="0"/>
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<field name="Z" start="1" end="1"/>
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<field name="S" start="2" end="2"/>
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<field name="O" start="3" end="3"/>
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<field name="I" start="16" end="16"/>
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<field name="U" start="17" end="17"/>
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<field name="PM" start="20" end="20"/>
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<field name="IPL" start="24" end="27"/>
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</flags>
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<flags id="fpsw_flags" size="4">
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<field name="RM" start="0" end="1"/>
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<field name="CV" start="2" end="2"/>
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<field name="CO" start="3" end="3"/>
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<field name="CZ" start="4" end="4"/>
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<field name="CU" start="5" end="5"/>
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<field name="CX" start="6" end="6"/>
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<field name="CE" start="7" end="7"/>
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<field name="DN" start="8" end="8"/>
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<field name="EV" start="10" end="10"/>
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<field name="EO" start="11" end="11"/>
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<field name="EZ" start="12" end="12"/>
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<field name="EU" start="13" end="13"/>
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<field name="EX" start="14" end="14"/>
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<field name="FV" start="26" end="26"/>
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<field name="FO" start="27" end="27"/>
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<field name="FZ" start="28" end="28"/>
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<field name="FU" start="29" end="29"/>
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<field name="FX" start="30" end="30"/>
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<field name="FS" start="31" end="31"/>
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</flags>
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<reg name="usp" bitsize="32" type="data_ptr"/>
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<reg name="isp" bitsize="32" type="data_ptr"/>
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<reg name="psw" bitsize="32" type="psw_flags"/>
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<reg name="pc" bitsize="32" type="code_ptr"/>
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<reg name="intb" bitsize="32" type="data_ptr"/>
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<reg name="bpsw" bitsize="32" type="psw_flags"/>
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<reg name="bpc" bitsize="32" type="code_ptr"/>
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<reg name="fintv" bitsize="32" type="code_ptr"/>
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<reg name="fpsw" bitsize="32" type="fpsw_flags"/>
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<reg name="acc" bitsize="64" type="uint64"/>
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</feature>
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@ -1,5 +1,4 @@
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obj-y += translate.o op_helper.o helper.o cpu.o gdbstub.o disas.o
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obj-y += translate.o op_helper.o helper.o cpu.o gdbstub.o disas.o
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obj-$(CONFIG_SOFTMMU) += monitor.o
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DECODETREE = $(SRC_PATH)/scripts/decodetree.py
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DECODETREE = $(SRC_PATH)/scripts/decodetree.py
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30
target/rx/cpu-param.h
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30
target/rx/cpu-param.h
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/*
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* RX cpu parameters
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*
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* Copyright (c) 2019 Yoshinori Sato
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef RX_CPU_PARAM_H
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#define RX_CPU_PARAM_H
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#define TARGET_LONG_BITS 32
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#define TARGET_PAGE_BITS 12
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#define TARGET_PHYS_ADDR_SPACE_BITS 32
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#define TARGET_VIRT_ADDR_SPACE_BITS 32
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#define NB_MMU_MODES 1
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#endif
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53
target/rx/cpu-qom.h
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53
target/rx/cpu-qom.h
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/*
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* RX CPU
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*
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* Copyright (c) 2019 Yoshinori Sato
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef RX_CPU_QOM_H
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#define RX_CPU_QOM_H
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#include "hw/core/cpu.h"
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#define TYPE_RX_CPU "rx-cpu"
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#define TYPE_RX62N_CPU RX_CPU_TYPE_NAME("rx62n")
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#define RXCPU_CLASS(klass) \
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OBJECT_CLASS_CHECK(RXCPUClass, (klass), TYPE_RX_CPU)
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#define RXCPU(obj) \
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OBJECT_CHECK(RXCPU, (obj), TYPE_RX_CPU)
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#define RXCPU_GET_CLASS(obj) \
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OBJECT_GET_CLASS(RXCPUClass, (obj), TYPE_RX_CPU)
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/*
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* RXCPUClass:
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* @parent_realize: The parent class' realize handler.
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* @parent_reset: The parent class' reset handler.
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*
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* A RX CPU model.
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*/
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typedef struct RXCPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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DeviceRealize parent_realize;
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DeviceReset parent_reset;
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} RXCPUClass;
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#define CPUArchState struct CPURXState
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#endif
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225
target/rx/cpu.c
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225
target/rx/cpu.c
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@ -0,0 +1,225 @@
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/*
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* QEMU RX CPU
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*
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* Copyright (c) 2019 Yoshinori Sato
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/qemu-print.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "qemu-common.h"
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#include "migration/vmstate.h"
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#include "exec/exec-all.h"
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#include "hw/loader.h"
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#include "fpu/softfloat.h"
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static void rx_cpu_set_pc(CPUState *cs, vaddr value)
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{
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RXCPU *cpu = RXCPU(cs);
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cpu->env.pc = value;
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}
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static void rx_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
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{
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RXCPU *cpu = RXCPU(cs);
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cpu->env.pc = tb->pc;
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}
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static bool rx_cpu_has_work(CPUState *cs)
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{
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return cs->interrupt_request &
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(CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR);
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}
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static void rx_cpu_reset(DeviceState *dev)
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{
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RXCPU *cpu = RXCPU(dev);
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RXCPUClass *rcc = RXCPU_GET_CLASS(cpu);
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CPURXState *env = &cpu->env;
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uint32_t *resetvec;
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rcc->parent_reset(dev);
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memset(env, 0, offsetof(CPURXState, end_reset_fields));
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resetvec = rom_ptr(0xfffffffc, 4);
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if (resetvec) {
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/* In the case of kernel, it is ignored because it is not set. */
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env->pc = ldl_p(resetvec);
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}
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rx_cpu_unpack_psw(env, 0, 1);
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env->regs[0] = env->isp = env->usp = 0;
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env->fpsw = 0;
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set_flush_to_zero(1, &env->fp_status);
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set_flush_inputs_to_zero(1, &env->fp_status);
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}
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static void rx_cpu_list_entry(gpointer data, gpointer user_data)
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{
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ObjectClass *oc = data;
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qemu_printf(" %s\n", object_class_get_name(oc));
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}
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void rx_cpu_list(void)
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{
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GSList *list;
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list = object_class_get_list_sorted(TYPE_RX_CPU, false);
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qemu_printf("Available CPUs:\n");
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g_slist_foreach(list, rx_cpu_list_entry, NULL);
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g_slist_free(list);
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}
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static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
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char *typename;
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oc = object_class_by_name(cpu_model);
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if (oc != NULL && object_class_dynamic_cast(oc, TYPE_RX_CPU) != NULL &&
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!object_class_is_abstract(oc)) {
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return oc;
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}
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typename = g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model);
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oc = object_class_by_name(typename);
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g_free(typename);
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if (oc != NULL && object_class_is_abstract(oc)) {
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oc = NULL;
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}
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return oc;
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}
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static void rx_cpu_realize(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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RXCPUClass *rcc = RXCPU_GET_CLASS(dev);
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Error *local_err = NULL;
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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qemu_init_vcpu(cs);
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cpu_reset(cs);
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rcc->parent_realize(dev, errp);
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}
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static void rx_cpu_set_irq(void *opaque, int no, int request)
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{
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RXCPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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int irq = request & 0xff;
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static const int mask[] = {
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[RX_CPU_IRQ] = CPU_INTERRUPT_HARD,
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[RX_CPU_FIR] = CPU_INTERRUPT_FIR,
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};
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if (irq) {
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cpu->env.req_irq = irq;
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cpu->env.req_ipl = (request >> 8) & 0x0f;
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cpu_interrupt(cs, mask[no]);
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} else {
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cpu_reset_interrupt(cs, mask[no]);
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}
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}
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static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
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{
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info->mach = bfd_mach_rx;
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info->print_insn = print_insn_rx;
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}
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static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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uint32_t address, physical, prot;
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/* Linear mapping */
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address = physical = addr & TARGET_PAGE_MASK;
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
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return true;
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}
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static void rx_cpu_init(Object *obj)
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{
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CPUState *cs = CPU(obj);
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RXCPU *cpu = RXCPU(obj);
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CPURXState *env = &cpu->env;
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cpu_set_cpustate_pointers(cpu);
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cs->env_ptr = env;
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qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
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}
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static void rx_cpu_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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CPUClass *cc = CPU_CLASS(klass);
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RXCPUClass *rcc = RXCPU_CLASS(klass);
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device_class_set_parent_realize(dc, rx_cpu_realize,
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&rcc->parent_realize);
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device_class_set_parent_reset(dc, rx_cpu_reset,
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&rcc->parent_reset);
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cc->class_by_name = rx_cpu_class_by_name;
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||||||
|
cc->has_work = rx_cpu_has_work;
|
||||||
|
cc->do_interrupt = rx_cpu_do_interrupt;
|
||||||
|
cc->cpu_exec_interrupt = rx_cpu_exec_interrupt;
|
||||||
|
cc->dump_state = rx_cpu_dump_state;
|
||||||
|
cc->set_pc = rx_cpu_set_pc;
|
||||||
|
cc->synchronize_from_tb = rx_cpu_synchronize_from_tb;
|
||||||
|
cc->gdb_read_register = rx_cpu_gdb_read_register;
|
||||||
|
cc->gdb_write_register = rx_cpu_gdb_write_register;
|
||||||
|
cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
|
||||||
|
cc->disas_set_info = rx_cpu_disas_set_info;
|
||||||
|
cc->tcg_initialize = rx_translate_init;
|
||||||
|
cc->tlb_fill = rx_cpu_tlb_fill;
|
||||||
|
|
||||||
|
cc->gdb_num_core_regs = 26;
|
||||||
|
cc->gdb_core_xml_file = "rx-core.xml";
|
||||||
|
}
|
||||||
|
|
||||||
|
static const TypeInfo rx_cpu_info = {
|
||||||
|
.name = TYPE_RX_CPU,
|
||||||
|
.parent = TYPE_CPU,
|
||||||
|
.instance_size = sizeof(RXCPU),
|
||||||
|
.instance_init = rx_cpu_init,
|
||||||
|
.abstract = true,
|
||||||
|
.class_size = sizeof(RXCPUClass),
|
||||||
|
.class_init = rx_cpu_class_init,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const TypeInfo rx62n_rx_cpu_info = {
|
||||||
|
.name = TYPE_RX62N_CPU,
|
||||||
|
.parent = TYPE_RX_CPU,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void rx_cpu_register_types(void)
|
||||||
|
{
|
||||||
|
type_register_static(&rx_cpu_info);
|
||||||
|
type_register_static(&rx62n_rx_cpu_info);
|
||||||
|
}
|
||||||
|
|
||||||
|
type_init(rx_cpu_register_types)
|
||||||
180
target/rx/cpu.h
Normal file
180
target/rx/cpu.h
Normal file
@ -0,0 +1,180 @@
|
|||||||
|
/*
|
||||||
|
* RX emulation definition
|
||||||
|
*
|
||||||
|
* Copyright (c) 2019 Yoshinori Sato
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2 or later, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License along with
|
||||||
|
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef RX_CPU_H
|
||||||
|
#define RX_CPU_H
|
||||||
|
|
||||||
|
#include "qemu/bitops.h"
|
||||||
|
#include "qemu-common.h"
|
||||||
|
#include "hw/registerfields.h"
|
||||||
|
#include "cpu-qom.h"
|
||||||
|
|
||||||
|
#include "exec/cpu-defs.h"
|
||||||
|
|
||||||
|
/* PSW define */
|
||||||
|
REG32(PSW, 0)
|
||||||
|
FIELD(PSW, C, 0, 1)
|
||||||
|
FIELD(PSW, Z, 1, 1)
|
||||||
|
FIELD(PSW, S, 2, 1)
|
||||||
|
FIELD(PSW, O, 3, 1)
|
||||||
|
FIELD(PSW, I, 16, 1)
|
||||||
|
FIELD(PSW, U, 17, 1)
|
||||||
|
FIELD(PSW, PM, 20, 1)
|
||||||
|
FIELD(PSW, IPL, 24, 4)
|
||||||
|
|
||||||
|
/* FPSW define */
|
||||||
|
REG32(FPSW, 0)
|
||||||
|
FIELD(FPSW, RM, 0, 2)
|
||||||
|
FIELD(FPSW, CV, 2, 1)
|
||||||
|
FIELD(FPSW, CO, 3, 1)
|
||||||
|
FIELD(FPSW, CZ, 4, 1)
|
||||||
|
FIELD(FPSW, CU, 5, 1)
|
||||||
|
FIELD(FPSW, CX, 6, 1)
|
||||||
|
FIELD(FPSW, CE, 7, 1)
|
||||||
|
FIELD(FPSW, CAUSE, 2, 6)
|
||||||
|
FIELD(FPSW, DN, 8, 1)
|
||||||
|
FIELD(FPSW, EV, 10, 1)
|
||||||
|
FIELD(FPSW, EO, 11, 1)
|
||||||
|
FIELD(FPSW, EZ, 12, 1)
|
||||||
|
FIELD(FPSW, EU, 13, 1)
|
||||||
|
FIELD(FPSW, EX, 14, 1)
|
||||||
|
FIELD(FPSW, ENABLE, 10, 5)
|
||||||
|
FIELD(FPSW, FV, 26, 1)
|
||||||
|
FIELD(FPSW, FO, 27, 1)
|
||||||
|
FIELD(FPSW, FZ, 28, 1)
|
||||||
|
FIELD(FPSW, FU, 29, 1)
|
||||||
|
FIELD(FPSW, FX, 30, 1)
|
||||||
|
FIELD(FPSW, FLAGS, 26, 4)
|
||||||
|
FIELD(FPSW, FS, 31, 1)
|
||||||
|
|
||||||
|
enum {
|
||||||
|
NUM_REGS = 16,
|
||||||
|
};
|
||||||
|
|
||||||
|
typedef struct CPURXState {
|
||||||
|
/* CPU registers */
|
||||||
|
uint32_t regs[NUM_REGS]; /* general registers */
|
||||||
|
uint32_t psw_o; /* O bit of status register */
|
||||||
|
uint32_t psw_s; /* S bit of status register */
|
||||||
|
uint32_t psw_z; /* Z bit of status register */
|
||||||
|
uint32_t psw_c; /* C bit of status register */
|
||||||
|
uint32_t psw_u;
|
||||||
|
uint32_t psw_i;
|
||||||
|
uint32_t psw_pm;
|
||||||
|
uint32_t psw_ipl;
|
||||||
|
uint32_t bpsw; /* backup status */
|
||||||
|
uint32_t bpc; /* backup pc */
|
||||||
|
uint32_t isp; /* global base register */
|
||||||
|
uint32_t usp; /* vector base register */
|
||||||
|
uint32_t pc; /* program counter */
|
||||||
|
uint32_t intb; /* interrupt vector */
|
||||||
|
uint32_t fintv;
|
||||||
|
uint32_t fpsw;
|
||||||
|
uint64_t acc;
|
||||||
|
|
||||||
|
/* Fields up to this point are cleared by a CPU reset */
|
||||||
|
struct {} end_reset_fields;
|
||||||
|
|
||||||
|
/* Internal use */
|
||||||
|
uint32_t in_sleep;
|
||||||
|
uint32_t req_irq; /* Requested interrupt no (hard) */
|
||||||
|
uint32_t req_ipl; /* Requested interrupt level */
|
||||||
|
uint32_t ack_irq; /* execute irq */
|
||||||
|
uint32_t ack_ipl; /* execute ipl */
|
||||||
|
float_status fp_status;
|
||||||
|
qemu_irq ack; /* Interrupt acknowledge */
|
||||||
|
} CPURXState;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* RXCPU:
|
||||||
|
* @env: #CPURXState
|
||||||
|
*
|
||||||
|
* A RX CPU
|
||||||
|
*/
|
||||||
|
struct RXCPU {
|
||||||
|
/*< private >*/
|
||||||
|
CPUState parent_obj;
|
||||||
|
/*< public >*/
|
||||||
|
|
||||||
|
CPUNegativeOffsetState neg;
|
||||||
|
CPURXState env;
|
||||||
|
};
|
||||||
|
|
||||||
|
typedef struct RXCPU RXCPU;
|
||||||
|
typedef RXCPU ArchCPU;
|
||||||
|
|
||||||
|
#define ENV_OFFSET offsetof(RXCPU, env)
|
||||||
|
|
||||||
|
#define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU
|
||||||
|
#define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX
|
||||||
|
#define CPU_RESOLVING_TYPE TYPE_RX_CPU
|
||||||
|
|
||||||
|
const char *rx_crname(uint8_t cr);
|
||||||
|
void rx_cpu_do_interrupt(CPUState *cpu);
|
||||||
|
bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req);
|
||||||
|
void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
|
||||||
|
int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
|
||||||
|
int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
|
||||||
|
hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
|
||||||
|
|
||||||
|
void rx_translate_init(void);
|
||||||
|
int cpu_rx_signal_handler(int host_signum, void *pinfo,
|
||||||
|
void *puc);
|
||||||
|
|
||||||
|
void rx_cpu_list(void);
|
||||||
|
void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte);
|
||||||
|
|
||||||
|
#define cpu_signal_handler cpu_rx_signal_handler
|
||||||
|
#define cpu_list rx_cpu_list
|
||||||
|
|
||||||
|
#include "exec/cpu-all.h"
|
||||||
|
|
||||||
|
#define CPU_INTERRUPT_SOFT CPU_INTERRUPT_TGT_INT_0
|
||||||
|
#define CPU_INTERRUPT_FIR CPU_INTERRUPT_TGT_INT_1
|
||||||
|
|
||||||
|
#define RX_CPU_IRQ 0
|
||||||
|
#define RX_CPU_FIR 1
|
||||||
|
|
||||||
|
static inline void cpu_get_tb_cpu_state(CPURXState *env, target_ulong *pc,
|
||||||
|
target_ulong *cs_base, uint32_t *flags)
|
||||||
|
{
|
||||||
|
*pc = env->pc;
|
||||||
|
*cs_base = 0;
|
||||||
|
*flags = FIELD_DP32(0, PSW, PM, env->psw_pm);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline int cpu_mmu_index(CPURXState *env, bool ifetch)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline uint32_t rx_cpu_pack_psw(CPURXState *env)
|
||||||
|
{
|
||||||
|
uint32_t psw = 0;
|
||||||
|
psw = FIELD_DP32(psw, PSW, IPL, env->psw_ipl);
|
||||||
|
psw = FIELD_DP32(psw, PSW, PM, env->psw_pm);
|
||||||
|
psw = FIELD_DP32(psw, PSW, U, env->psw_u);
|
||||||
|
psw = FIELD_DP32(psw, PSW, I, env->psw_i);
|
||||||
|
psw = FIELD_DP32(psw, PSW, O, env->psw_o >> 31);
|
||||||
|
psw = FIELD_DP32(psw, PSW, S, env->psw_s >> 31);
|
||||||
|
psw = FIELD_DP32(psw, PSW, Z, env->psw_z == 0);
|
||||||
|
psw = FIELD_DP32(psw, PSW, C, env->psw_c);
|
||||||
|
return psw;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* RX_CPU_H */
|
||||||
112
target/rx/gdbstub.c
Normal file
112
target/rx/gdbstub.c
Normal file
@ -0,0 +1,112 @@
|
|||||||
|
/*
|
||||||
|
* RX gdb server stub
|
||||||
|
*
|
||||||
|
* Copyright (c) 2019 Yoshinori Sato
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2 or later, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License along with
|
||||||
|
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
#include "qemu/osdep.h"
|
||||||
|
#include "qemu-common.h"
|
||||||
|
#include "cpu.h"
|
||||||
|
#include "exec/gdbstub.h"
|
||||||
|
|
||||||
|
int rx_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
|
||||||
|
{
|
||||||
|
RXCPU *cpu = RXCPU(cs);
|
||||||
|
CPURXState *env = &cpu->env;
|
||||||
|
|
||||||
|
switch (n) {
|
||||||
|
case 0 ... 15:
|
||||||
|
return gdb_get_regl(mem_buf, env->regs[n]);
|
||||||
|
case 16:
|
||||||
|
return gdb_get_regl(mem_buf, (env->psw_u) ? env->regs[0] : env->usp);
|
||||||
|
case 17:
|
||||||
|
return gdb_get_regl(mem_buf, (!env->psw_u) ? env->regs[0] : env->isp);
|
||||||
|
case 18:
|
||||||
|
return gdb_get_regl(mem_buf, rx_cpu_pack_psw(env));
|
||||||
|
case 19:
|
||||||
|
return gdb_get_regl(mem_buf, env->pc);
|
||||||
|
case 20:
|
||||||
|
return gdb_get_regl(mem_buf, env->intb);
|
||||||
|
case 21:
|
||||||
|
return gdb_get_regl(mem_buf, env->bpsw);
|
||||||
|
case 22:
|
||||||
|
return gdb_get_regl(mem_buf, env->bpc);
|
||||||
|
case 23:
|
||||||
|
return gdb_get_regl(mem_buf, env->fintv);
|
||||||
|
case 24:
|
||||||
|
return gdb_get_regl(mem_buf, env->fpsw);
|
||||||
|
case 25:
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int rx_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
|
||||||
|
{
|
||||||
|
RXCPU *cpu = RXCPU(cs);
|
||||||
|
CPURXState *env = &cpu->env;
|
||||||
|
uint32_t psw;
|
||||||
|
switch (n) {
|
||||||
|
case 0 ... 15:
|
||||||
|
env->regs[n] = ldl_p(mem_buf);
|
||||||
|
if (n == 0) {
|
||||||
|
if (env->psw_u) {
|
||||||
|
env->usp = env->regs[0];
|
||||||
|
} else {
|
||||||
|
env->isp = env->regs[0];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case 16:
|
||||||
|
env->usp = ldl_p(mem_buf);
|
||||||
|
if (env->psw_u) {
|
||||||
|
env->regs[0] = ldl_p(mem_buf);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case 17:
|
||||||
|
env->isp = ldl_p(mem_buf);
|
||||||
|
if (!env->psw_u) {
|
||||||
|
env->regs[0] = ldl_p(mem_buf);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case 18:
|
||||||
|
psw = ldl_p(mem_buf);
|
||||||
|
rx_cpu_unpack_psw(env, psw, 1);
|
||||||
|
break;
|
||||||
|
case 19:
|
||||||
|
env->pc = ldl_p(mem_buf);
|
||||||
|
break;
|
||||||
|
case 20:
|
||||||
|
env->intb = ldl_p(mem_buf);
|
||||||
|
break;
|
||||||
|
case 21:
|
||||||
|
env->bpsw = ldl_p(mem_buf);
|
||||||
|
break;
|
||||||
|
case 22:
|
||||||
|
env->bpc = ldl_p(mem_buf);
|
||||||
|
break;
|
||||||
|
case 23:
|
||||||
|
env->fintv = ldl_p(mem_buf);
|
||||||
|
break;
|
||||||
|
case 24:
|
||||||
|
env->fpsw = ldl_p(mem_buf);
|
||||||
|
break;
|
||||||
|
case 25:
|
||||||
|
return 8;
|
||||||
|
default:
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 4;
|
||||||
|
}
|
||||||
@ -41,10 +41,17 @@ typedef struct DisasCompare {
|
|||||||
TCGCond cond;
|
TCGCond cond;
|
||||||
} DisasCompare;
|
} DisasCompare;
|
||||||
|
|
||||||
const char rx_crname[][6] = {
|
const char *rx_crname(uint8_t cr)
|
||||||
"psw", "pc", "usp", "fpsw", "", "", "", "",
|
{
|
||||||
"bpsw", "bpc", "isp", "fintv", "intb", "", "", "",
|
static const char *cr_names[] = {
|
||||||
};
|
"psw", "pc", "usp", "fpsw", "", "", "", "",
|
||||||
|
"bpsw", "bpc", "isp", "fintv", "intb", "", "", ""
|
||||||
|
};
|
||||||
|
if (cr >= ARRAY_SIZE(cr_names)) {
|
||||||
|
return "illegal";
|
||||||
|
}
|
||||||
|
return cr_names[cr];
|
||||||
|
}
|
||||||
|
|
||||||
/* Target-specific values for dc->base.is_jmp. */
|
/* Target-specific values for dc->base.is_jmp. */
|
||||||
#define DISAS_JUMP DISAS_TARGET_0
|
#define DISAS_JUMP DISAS_TARGET_0
|
||||||
@ -365,7 +372,7 @@ static void move_to_cr(DisasContext *ctx, TCGv val, int cr)
|
|||||||
if (cr >= 8 && !is_privileged(ctx, 0)) {
|
if (cr >= 8 && !is_privileged(ctx, 0)) {
|
||||||
/* Some control registers can only be written in privileged mode. */
|
/* Some control registers can only be written in privileged mode. */
|
||||||
qemu_log_mask(LOG_GUEST_ERROR,
|
qemu_log_mask(LOG_GUEST_ERROR,
|
||||||
"disallow control register write %s", rx_crname[cr]);
|
"disallow control register write %s", rx_crname(cr));
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
z = tcg_const_i32(0);
|
z = tcg_const_i32(0);
|
||||||
|
|||||||
Loading…
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