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hw/arm/xilinx_zynq: fix the capabilities register to match the datasheet

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checking Xilinx datasheet "UG585" (v1.12.1)

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Message-Id: <20180208164818.7961-17-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2018-02-08 13:48:04 -03:00 committed by Paolo Bonzini
parent 2edb443471
commit 27a49d3be6
2 changed files with 32 additions and 22 deletions
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39
hw/arm/xilinx_zynq.c
View File

@ -61,6 +61,8 @@ static const int dma_irqs[8] = {
#define SLCR_XILINX_UNLOCK_KEY 0xdf0d #define SLCR_XILINX_UNLOCK_KEY 0xdf0d
#define SLCR_XILINX_LOCK_KEY 0x767b #define SLCR_XILINX_LOCK_KEY 0x767b
#define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */
#define ARMV7_IMM16(x) (extract32((x), 0, 12) | \ #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \
extract32((x), 12, 4) << 16) extract32((x), 12, 4) << 16)
@ -165,10 +167,8 @@ static void zynq_init(MachineState *machine)
MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ext_ram = g_new(MemoryRegion, 1); MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
DeviceState *dev, *carddev; DeviceState *dev;
SysBusDevice *busdev; SysBusDevice *busdev;
DriveInfo *di;
BlockBackend *blk;
qemu_irq pic[64]; qemu_irq pic[64];
int n; int n;
@ -247,27 +247,32 @@ static void zynq_init(MachineState *machine)
gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]); gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]);
gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]); gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]);
for (n = 0; n < 2; n++) {
int hci_irq = n ? 79 : 56;
hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000;
DriveInfo *di;
BlockBackend *blk;
DeviceState *carddev;
/* Compatible with:
* - SD Host Controller Specification Version 2.0 Part A2
* - SDIO Specification Version 2.0
* - MMC Specification Version 3.31
*/
dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI); dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);
qdev_prop_set_uint8(dev, "sd-spec-version", 2);
qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES);
qdev_init_nofail(dev); qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0100000); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[56-IRQ_OFFSET]); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]);
di = drive_get_next(IF_SD); di = drive_get_next(IF_SD);
blk = di ? blk_by_legacy_dinfo(di) : NULL; blk = di ? blk_by_legacy_dinfo(di) : NULL;
carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD); carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal); object_property_set_bool(OBJECT(carddev), true, "realized",
&error_fatal);
dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI); }
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79-IRQ_OFFSET]);
di = drive_get_next(IF_SD);
blk = di ? blk_by_legacy_dinfo(di) : NULL;
carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
dev = qdev_create(NULL, TYPE_ZYNQ_XADC); dev = qdev_create(NULL, TYPE_ZYNQ_XADC);
qdev_init_nofail(dev); qdev_init_nofail(dev);

5
tests/sdhci-test.c
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@ -41,6 +41,11 @@ static const struct sdhci_t {
/* Exynos4210 */ /* Exynos4210 */
{ "arm", "smdkc210", { "arm", "smdkc210",
{0x12510000, 2, 0, {1, 0x5e80080} } }, {0x12510000, 2, 0, {1, 0x5e80080} } },
/* Zynq-7000 */
{ "arm", "xilinx-zynq-a9", /* Datasheet: UG585 (v1.12.1) */
{0xe0100000, 2, 0, {1, 0x69ec0080} } },
}; };
typedef struct QSDHCI { typedef struct QSDHCI {