target/ppc: add power-saving interrupt masking logic to p9_next_unmasked_interrupt
Export p9_interrupt_powersave and use it in p9_next_unmasked_interrupt. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20221011204829.1641124-12-matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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@ -6351,7 +6351,7 @@ static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
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return false;
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}
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static int p9_interrupt_powersave(CPUPPCState *env)
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int p9_interrupt_powersave(CPUPPCState *env)
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{
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/* External Exception */
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if ((env->pending_interrupts & PPC_INTERRUPT_EXT) &&
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@ -1692,28 +1692,39 @@ void ppc_cpu_do_interrupt(CPUState *cs)
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static int p9_next_unmasked_interrupt(CPUPPCState *env)
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{
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bool async_deliver;
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PowerPCCPU *cpu = env_archcpu(env);
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CPUState *cs = CPU(cpu);
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/* Ignore MSR[EE] when coming out of some power management states */
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bool msr_ee = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset;
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assert((env->pending_interrupts & P9_UNUSED_INTERRUPTS) == 0);
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if (cs->halted) {
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if (env->spr[SPR_PSSCR] & PSSCR_EC) {
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/*
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* When PSSCR[EC] is set, LPCR[PECE] controls which interrupts can
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* wakeup the processor
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*/
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return p9_interrupt_powersave(env);
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} else {
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/*
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* When it's clear, any system-caused exception exits power-saving
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* mode, even the ones that gate on MSR[EE].
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*/
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msr_ee = true;
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}
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}
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/* Machine check exception */
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if (env->pending_interrupts & PPC_INTERRUPT_MCK) {
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return PPC_INTERRUPT_MCK;
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}
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/*
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* For interrupts that gate on MSR:EE, we need to do something a
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* bit more subtle, as we need to let them through even when EE is
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* clear when coming out of some power management states (in order
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* for them to become a 0x100).
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*/
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async_deliver = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset;
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/* Hypervisor decrementer exception */
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if (env->pending_interrupts & PPC_INTERRUPT_HDECR) {
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/* LPCR will be clear when not supported so this will work */
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bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE);
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if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hdice) {
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if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hdice) {
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/* HDEC clears on delivery */
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return PPC_INTERRUPT_HDECR;
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}
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@ -1723,7 +1734,7 @@ static int p9_next_unmasked_interrupt(CPUPPCState *env)
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if (env->pending_interrupts & PPC_INTERRUPT_HVIRT) {
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/* LPCR will be clear when not supported so this will work */
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bool hvice = !!(env->spr[SPR_LPCR] & LPCR_HVICE);
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if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hvice) {
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if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hvice) {
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return PPC_INTERRUPT_HVIRT;
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}
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}
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@ -1733,13 +1744,13 @@ static int p9_next_unmasked_interrupt(CPUPPCState *env)
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bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
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bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
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/* HEIC blocks delivery to the hypervisor */
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if ((async_deliver && !(heic && FIELD_EX64_HV(env->msr) &&
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if ((msr_ee && !(heic && FIELD_EX64_HV(env->msr) &&
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!FIELD_EX64(env->msr, MSR, PR))) ||
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(env->has_hv_mode && !FIELD_EX64_HV(env->msr) && !lpes0)) {
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return PPC_INTERRUPT_EXT;
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}
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}
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if (async_deliver != 0) {
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if (msr_ee != 0) {
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/* Decrementer exception */
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if (env->pending_interrupts & PPC_INTERRUPT_DECR) {
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return PPC_INTERRUPT_DECR;
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@ -1901,6 +1912,15 @@ static void p9_deliver_interrupt(CPUPPCState *env, int interrupt)
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PowerPCCPU *cpu = env_archcpu(env);
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CPUState *cs = env_cpu(env);
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if (cs->halted && !(env->spr[SPR_PSSCR] & PSSCR_EC) &&
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!FIELD_EX64(env->msr, MSR, EE)) {
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/*
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* A pending interrupt took us out of power-saving, but MSR[EE] says
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* that we should return to NIP+4 instead of delivering it.
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*/
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return;
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}
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switch (interrupt) {
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case PPC_INTERRUPT_MCK: /* Machine check exception */
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env->pending_interrupts &= ~PPC_INTERRUPT_MCK;
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@ -306,4 +306,8 @@ static inline int ger_pack_masks(int pmsk, int ymsk, int xmsk)
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return msk;
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}
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#if defined(TARGET_PPC64)
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int p9_interrupt_powersave(CPUPPCState *env);
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#endif
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#endif /* PPC_INTERNAL_H */
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