target-arm: Convert cp15 crn=1 registers
Convert the cp15 crn=1 registers to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
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34f9052967
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2771db2741
@ -97,6 +97,7 @@ typedef struct ARMCPU {
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*/
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*/
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uint32_t ccsidr[16];
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uint32_t ccsidr[16];
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uint32_t reset_cbar;
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uint32_t reset_cbar;
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uint32_t reset_auxcr;
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} ARMCPU;
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} ARMCPU;
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static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
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static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
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@ -77,7 +77,6 @@ static void arm_cpu_reset(CPUState *s)
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env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
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env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
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env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
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env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
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env->cp15.c0_cachetype = cpu->ctr;
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env->cp15.c0_cachetype = cpu->ctr;
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env->cp15.c1_sys = cpu->reset_sctlr;
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env->cp15.c0_c1[0] = cpu->id_pfr0;
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env->cp15.c0_c1[0] = cpu->id_pfr0;
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env->cp15.c0_c1[1] = cpu->id_pfr1;
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env->cp15.c0_c1[1] = cpu->id_pfr1;
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env->cp15.c0_c1[2] = cpu->id_dfr0;
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env->cp15.c0_c1[2] = cpu->id_dfr0;
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@ -252,6 +251,7 @@ static void arm1026_initfn(Object *obj)
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cpu->reset_fpsid = 0x410110a0;
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cpu->reset_fpsid = 0x410110a0;
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cpu->ctr = 0x1dd20d2;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00090078;
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cpu->reset_sctlr = 0x00090078;
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cpu->reset_auxcr = 1;
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{
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{
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/* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
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/* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
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ARMCPRegInfo ifar = {
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ARMCPRegInfo ifar = {
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@ -297,6 +297,7 @@ static void arm1136_r2_initfn(Object *obj)
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cpu->id_isar2 = 0x11231111;
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cpu->id_isar2 = 0x11231111;
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cpu->id_isar3 = 0x01102131;
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cpu->id_isar3 = 0x01102131;
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cpu->id_isar4 = 0x141;
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cpu->id_isar4 = 0x141;
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cpu->reset_auxcr = 7;
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}
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}
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static void arm1136_initfn(Object *obj)
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static void arm1136_initfn(Object *obj)
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@ -326,6 +327,7 @@ static void arm1136_initfn(Object *obj)
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cpu->id_isar2 = 0x11231111;
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cpu->id_isar2 = 0x11231111;
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cpu->id_isar3 = 0x01102131;
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cpu->id_isar3 = 0x01102131;
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cpu->id_isar4 = 0x141;
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cpu->id_isar4 = 0x141;
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cpu->reset_auxcr = 7;
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}
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}
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static void arm1176_initfn(Object *obj)
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static void arm1176_initfn(Object *obj)
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@ -355,6 +357,7 @@ static void arm1176_initfn(Object *obj)
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cpu->id_isar2 = 0x11231121;
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cpu->id_isar2 = 0x11231121;
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cpu->id_isar3 = 0x01102131;
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cpu->id_isar3 = 0x01102131;
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cpu->id_isar4 = 0x01141;
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cpu->id_isar4 = 0x01141;
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cpu->reset_auxcr = 7;
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}
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}
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static void arm11mpcore_initfn(Object *obj)
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static void arm11mpcore_initfn(Object *obj)
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@ -381,6 +384,7 @@ static void arm11mpcore_initfn(Object *obj)
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cpu->id_isar2 = 0x11221011;
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cpu->id_isar2 = 0x11221011;
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cpu->id_isar3 = 0x01102131;
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cpu->id_isar3 = 0x01102131;
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cpu->id_isar4 = 0x141;
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cpu->id_isar4 = 0x141;
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cpu->reset_auxcr = 1;
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}
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}
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static void cortex_m3_initfn(Object *obj)
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static void cortex_m3_initfn(Object *obj)
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@ -430,6 +434,7 @@ static void cortex_a8_initfn(Object *obj)
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cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
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cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
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cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
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cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
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cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
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cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
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cpu->reset_auxcr = 2;
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define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
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define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
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}
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}
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@ -196,6 +196,16 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = {
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REGINFO_SENTINEL
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REGINFO_SENTINEL
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};
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};
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static int cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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{
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if (env->cp15.c1_coproc != value) {
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env->cp15.c1_coproc = value;
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/* ??? Is this safe when called from within a TB? */
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tb_flush(env);
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}
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return 0;
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}
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static const ARMCPRegInfo v6_cp_reginfo[] = {
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static const ARMCPRegInfo v6_cp_reginfo[] = {
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/* prefetch by MVA in v6, NOP in v7 */
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/* prefetch by MVA in v6, NOP in v7 */
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{ .name = "MVA_prefetch",
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{ .name = "MVA_prefetch",
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@ -215,6 +225,9 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
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*/
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*/
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{ .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
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{ .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
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{ .name = "CPACR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
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.resetvalue = 0, .writefn = cpacr_write },
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REGINFO_SENTINEL
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REGINFO_SENTINEL
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};
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};
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@ -376,6 +389,9 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
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.resetvalue = 0,
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.resetvalue = 0,
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.writefn = pmintenclr_write },
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.writefn = pmintenclr_write },
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{ .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
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.resetvalue = 0, },
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REGINFO_SENTINEL
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REGINFO_SENTINEL
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};
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};
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@ -736,6 +752,10 @@ static const ARMCPRegInfo xscale_cp_reginfo[] = {
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.cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
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.cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
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.fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
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.fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
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.writefn = xscale_cpar_write, },
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.writefn = xscale_cpar_write, },
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{ .name = "XSCALE_AUXCR",
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.cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
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.fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
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.resetvalue = 0, },
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REGINFO_SENTINEL
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REGINFO_SENTINEL
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};
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};
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@ -785,6 +805,15 @@ static const ARMCPRegInfo strongarm_cp_reginfo[] = {
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REGINFO_SENTINEL
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REGINFO_SENTINEL
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};
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};
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static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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{
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env->cp15.c1_sys = value;
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/* ??? Lots of these bits are not implemented. */
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/* This may enable/disable the MMU, so do a TLB flush. */
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tlb_flush(env, 1);
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return 0;
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}
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void register_cp_regs_for_features(ARMCPU *cpu)
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void register_cp_regs_for_features(ARMCPU *cpu)
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{
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{
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/* Register all the coprocessor registers based on feature bits */
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/* Register all the coprocessor registers based on feature bits */
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@ -859,6 +888,31 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
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if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
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define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
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define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
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}
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}
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if (arm_feature(env, ARM_FEATURE_AUXCR)) {
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ARMCPRegInfo auxcr = {
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.name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
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.access = PL1_RW, .type = ARM_CP_CONST,
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.resetvalue = cpu->reset_auxcr
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};
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define_one_arm_cp_reg(cpu, &auxcr);
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}
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/* Generic registers whose values depend on the implementation */
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{
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ARMCPRegInfo sctlr = {
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.name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
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.writefn = sctlr_write, .resetvalue = cpu->reset_sctlr
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};
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if (arm_feature(env, ARM_FEATURE_XSCALE)) {
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/* Normally we would always end the TB on an SCTLR write, but Linux
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* arch/arm/mach-pxa/sleep.S expects two instructions following
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* an MMU enable to execute from cache. Imitate this behaviour.
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*/
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sctlr.type |= ARM_CP_SUPPRESS_TB_END;
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}
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define_one_arm_cp_reg(cpu, &sctlr);
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}
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}
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}
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ARMCPU *cpu_arm_init(const char *cpu_model)
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ARMCPU *cpu_arm_init(const char *cpu_model)
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@ -1949,42 +2003,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
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break;
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break;
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}
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}
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goto bad_reg;
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goto bad_reg;
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case 1: /* System configuration. */
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if (arm_feature(env, ARM_FEATURE_V7)
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&& op1 == 0 && crm == 1 && op2 == 0) {
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env->cp15.c1_scr = val;
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break;
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}
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if (arm_feature(env, ARM_FEATURE_OMAPCP))
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op2 = 0;
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switch (op2) {
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case 0:
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if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0)
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env->cp15.c1_sys = val;
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/* ??? Lots of these bits are not implemented. */
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/* This may enable/disable the MMU, so do a TLB flush. */
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tlb_flush(env, 1);
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break;
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case 1: /* Auxiliary control register. */
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if (arm_feature(env, ARM_FEATURE_XSCALE)) {
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env->cp15.c1_xscaleauxcr = val;
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break;
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}
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/* Not implemented. */
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break;
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case 2:
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if (arm_feature(env, ARM_FEATURE_XSCALE))
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goto bad_reg;
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if (env->cp15.c1_coproc != val) {
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env->cp15.c1_coproc = val;
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/* ??? Is this safe when called from within a TB? */
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tb_flush(env);
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}
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break;
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default:
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goto bad_reg;
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}
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break;
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case 4: /* Reserved. */
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case 4: /* Reserved. */
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goto bad_reg;
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goto bad_reg;
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case 12: /* Reserved. */
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case 12: /* Reserved. */
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@ -2085,45 +2103,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
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default:
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default:
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goto bad_reg;
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goto bad_reg;
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}
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}
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case 1: /* System configuration. */
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if (arm_feature(env, ARM_FEATURE_V7)
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&& op1 == 0 && crm == 1 && op2 == 0) {
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return env->cp15.c1_scr;
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}
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if (arm_feature(env, ARM_FEATURE_OMAPCP))
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op2 = 0;
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switch (op2) {
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case 0: /* Control register. */
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return env->cp15.c1_sys;
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case 1: /* Auxiliary control register. */
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if (arm_feature(env, ARM_FEATURE_XSCALE))
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return env->cp15.c1_xscaleauxcr;
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if (!arm_feature(env, ARM_FEATURE_AUXCR))
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goto bad_reg;
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switch (ARM_CPUID(env)) {
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case ARM_CPUID_ARM1026:
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return 1;
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case ARM_CPUID_ARM1136:
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case ARM_CPUID_ARM1136_R2:
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case ARM_CPUID_ARM1176:
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return 7;
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case ARM_CPUID_ARM11MPCORE:
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return 1;
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case ARM_CPUID_CORTEXA8:
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return 2;
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case ARM_CPUID_CORTEXA9:
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case ARM_CPUID_CORTEXA15:
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return 0;
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default:
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goto bad_reg;
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}
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case 2: /* Coprocessor access register. */
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if (arm_feature(env, ARM_FEATURE_XSCALE))
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goto bad_reg;
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return env->cp15.c1_coproc;
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default:
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goto bad_reg;
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}
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case 4: /* Reserved. */
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case 4: /* Reserved. */
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goto bad_reg;
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goto bad_reg;
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case 11: /* TCM DMA control. */
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case 11: /* TCM DMA control. */
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