hw/riscv: spike: Remove deprecated ISA specific machines
The ISA specific Spike machines have been deprecated in QEMU since 4.1, let's finally remove them. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Thomas Huth <thuth@redhat.com>
This commit is contained in:
Alistair Francis
parent
b2a3a071f7
commit
26cd0362dd
@ -379,13 +379,6 @@ This machine has been renamed ``fuloong2e``.
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These machine types are very old and likely can not be used for live migration
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These machine types are very old and likely can not be used for live migration
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from old QEMU versions anymore. A newer machine type should be used instead.
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from old QEMU versions anymore. A newer machine type should be used instead.
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``spike_v1.9.1`` and ``spike_v1.10`` (since 4.1)
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''''''''''''''''''''''''''''''''''''''''''''''''
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The version specific Spike machines have been deprecated in favour of the
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generic ``spike`` machine. If you need to specify an older version of the RISC-V
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spec you can use the ``-cpu rv64gcsu,priv_spec=v1.9.1`` command line argument.
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Device options
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Device options
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--------------
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--------------
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@ -493,6 +486,16 @@ The ``hub_id`` parameter of ``hostfwd_add`` / ``hostfwd_remove`` (removed in 5.0
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The ``[hub_id name]`` parameter tuple of the 'hostfwd_add' and
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The ``[hub_id name]`` parameter tuple of the 'hostfwd_add' and
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'hostfwd_remove' HMP commands has been replaced by ``netdev_id``.
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'hostfwd_remove' HMP commands has been replaced by ``netdev_id``.
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System emulator machines
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------------------------
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``spike_v1.9.1`` and ``spike_v1.10`` (removed in 5.1)
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'''''''''''''''''''''''''''''''''''''''''''''''''''''
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The version specific Spike machines have been removed in favour of the
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generic ``spike`` machine. If you need to specify an older version of the RISC-V
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spec you can use the ``-cpu rv64gcsu,priv_spec=v1.10.0`` command line argument.
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Related binaries
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Related binaries
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----------------
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----------------
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217
hw/riscv/spike.c
217
hw/riscv/spike.c
@ -257,221 +257,6 @@ static void spike_board_init(MachineState *machine)
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false);
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false);
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}
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}
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static void spike_v1_10_0_board_init(MachineState *machine)
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{
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const struct MemmapEntry *memmap = spike_memmap;
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SpikeState *s = g_new0(SpikeState, 1);
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *main_mem = g_new(MemoryRegion, 1);
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MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
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int i;
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unsigned int smp_cpus = machine->smp.cpus;
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if (!qtest_enabled()) {
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info_report("The Spike v1.10.0 machine has been deprecated. "
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"Please use the generic spike machine and specify the ISA "
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"versions using -cpu.");
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}
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/* Initialize SOC */
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object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
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TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
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object_property_set_str(OBJECT(&s->soc), SPIKE_V1_10_0_CPU, "cpu-type",
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&error_abort);
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object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
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&error_abort);
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object_property_set_bool(OBJECT(&s->soc), true, "realized",
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&error_abort);
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/* register system main memory (actual RAM) */
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memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
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machine->ram_size, &error_fatal);
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memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
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main_mem);
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/* create device tree */
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create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
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/* boot rom */
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memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
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memmap[SPIKE_MROM].size, &error_fatal);
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memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
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mask_rom);
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if (machine->kernel_filename) {
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riscv_load_kernel(machine->kernel_filename, htif_symbol_callback);
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}
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/* reset vector */
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uint32_t reset_vec[8] = {
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0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
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0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
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0xf1402573, /* csrr a0, mhartid */
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#if defined(TARGET_RISCV32)
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0x0182a283, /* lw t0, 24(t0) */
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#elif defined(TARGET_RISCV64)
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0x0182b283, /* ld t0, 24(t0) */
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#endif
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0x00028067, /* jr t0 */
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0x00000000,
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memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */
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0x00000000,
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/* dtb: */
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};
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/* copy in the reset vector in little_endian byte order */
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for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
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reset_vec[i] = cpu_to_le32(reset_vec[i]);
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}
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rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
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memmap[SPIKE_MROM].base, &address_space_memory);
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/* copy in the device tree */
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if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
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memmap[SPIKE_MROM].size - sizeof(reset_vec)) {
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error_report("not enough space to store device-tree");
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exit(1);
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}
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qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
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rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
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memmap[SPIKE_MROM].base + sizeof(reset_vec),
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&address_space_memory);
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/* initialize HTIF using symbols found in load_kernel */
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htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
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/* Core Local Interruptor (timer and IPI) */
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sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
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smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
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false);
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}
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static void spike_v1_09_1_board_init(MachineState *machine)
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{
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const struct MemmapEntry *memmap = spike_memmap;
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SpikeState *s = g_new0(SpikeState, 1);
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *main_mem = g_new(MemoryRegion, 1);
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MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
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int i;
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unsigned int smp_cpus = machine->smp.cpus;
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if (!qtest_enabled()) {
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info_report("The Spike v1.09.1 machine has been deprecated. "
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"Please use the generic spike machine and specify the ISA "
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"versions using -cpu.");
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}
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/* Initialize SOC */
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object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
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TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
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object_property_set_str(OBJECT(&s->soc), SPIKE_V1_09_1_CPU, "cpu-type",
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&error_abort);
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object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
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&error_abort);
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object_property_set_bool(OBJECT(&s->soc), true, "realized",
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&error_abort);
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/* register system main memory (actual RAM) */
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memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
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machine->ram_size, &error_fatal);
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memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
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main_mem);
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/* boot rom */
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memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
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memmap[SPIKE_MROM].size, &error_fatal);
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memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
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mask_rom);
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if (machine->kernel_filename) {
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riscv_load_kernel(machine->kernel_filename, htif_symbol_callback);
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}
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/* reset vector */
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uint32_t reset_vec[8] = {
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0x297 + memmap[SPIKE_DRAM].base - memmap[SPIKE_MROM].base, /* lui */
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0x00028067, /* jump to DRAM_BASE */
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0x00000000, /* reserved */
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memmap[SPIKE_MROM].base + sizeof(reset_vec), /* config string pointer */
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0, 0, 0, 0 /* trap vector */
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};
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/* part one of config string - before memory size specified */
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const char *config_string_tmpl =
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"platform {\n"
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" vendor ucb;\n"
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" arch spike;\n"
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"};\n"
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"rtc {\n"
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" addr 0x%" PRIx64 "x;\n"
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"};\n"
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"ram {\n"
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" 0 {\n"
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" addr 0x%" PRIx64 "x;\n"
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" size 0x%" PRIx64 "x;\n"
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" };\n"
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"};\n"
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"core {\n"
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" 0" " {\n"
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" " "0 {\n"
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" isa %s;\n"
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" timecmp 0x%" PRIx64 "x;\n"
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" ipi 0x%" PRIx64 "x;\n"
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" };\n"
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" };\n"
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"};\n";
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/* build config string with supplied memory size */
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char *isa = riscv_isa_string(&s->soc.harts[0]);
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char *config_string = g_strdup_printf(config_string_tmpl,
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(uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIME_BASE,
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(uint64_t)memmap[SPIKE_DRAM].base,
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(uint64_t)ram_size, isa,
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(uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIMECMP_BASE,
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(uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_SIP_BASE);
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g_free(isa);
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size_t config_string_len = strlen(config_string);
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/* copy in the reset vector in little_endian byte order */
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for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
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reset_vec[i] = cpu_to_le32(reset_vec[i]);
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}
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rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
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memmap[SPIKE_MROM].base, &address_space_memory);
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/* copy in the config string */
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rom_add_blob_fixed_as("mrom.reset", config_string, config_string_len,
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memmap[SPIKE_MROM].base + sizeof(reset_vec),
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&address_space_memory);
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/* initialize HTIF using symbols found in load_kernel */
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htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
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/* Core Local Interruptor (timer and IPI) */
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sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
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smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
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false);
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g_free(config_string);
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}
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static void spike_v1_09_1_machine_init(MachineClass *mc)
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{
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mc->desc = "RISC-V Spike Board (Privileged ISA v1.9.1)";
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mc->init = spike_v1_09_1_board_init;
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mc->max_cpus = 1;
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}
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static void spike_v1_10_0_machine_init(MachineClass *mc)
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{
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mc->desc = "RISC-V Spike Board (Privileged ISA v1.10)";
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mc->init = spike_v1_10_0_board_init;
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mc->max_cpus = 1;
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}
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static void spike_machine_init(MachineClass *mc)
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static void spike_machine_init(MachineClass *mc)
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{
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{
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mc->desc = "RISC-V Spike Board";
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mc->desc = "RISC-V Spike Board";
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@ -481,6 +266,4 @@ static void spike_machine_init(MachineClass *mc)
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mc->default_cpu_type = SPIKE_V1_10_0_CPU;
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mc->default_cpu_type = SPIKE_V1_10_0_CPU;
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}
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}
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DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init)
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DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init)
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DEFINE_MACHINE("spike", spike_machine_init)
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DEFINE_MACHINE("spike", spike_machine_init)
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@ -39,11 +39,9 @@ enum {
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};
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};
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#if defined(TARGET_RISCV32)
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#if defined(TARGET_RISCV32)
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#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1
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#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE32
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#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
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#elif defined(TARGET_RISCV64)
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#elif defined(TARGET_RISCV64)
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#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV64GCSU_V1_09_1
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#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE64
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#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0
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#endif
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#endif
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#endif
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#endif
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