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ppc: Create cpu_ppc_set_papr() helper

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And move the code adjusting the MSR mask and calling kvmppc_set_papr()
to it. This allows us to add a few more things such as disabling setting
of MSR:HV and appropriate LPCR bits which will be used when fixing
the exception model.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
[clg: removed LPCR setting ]
Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Benjamin Herrenschmidt 2016-03-21 13:52:34 +01:00 committed by David Gibson
parent f401dd32cb
commit 26a7f1291b
3 changed files with 25 additions and 10 deletions
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11
hw/ppc/spapr.c
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@ -1613,15 +1613,8 @@ static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu,
/* Set time-base frequency to 512 MHz */ /* Set time-base frequency to 512 MHz */
cpu_ppc_tb_init(env, TIMEBASE_FREQ); cpu_ppc_tb_init(env, TIMEBASE_FREQ);
/* PAPR always has exception vectors in RAM not ROM. To ensure this, /* Enable PAPR mode in TCG or KVM */
* MSR[IP] should never be set. cpu_ppc_set_papr(cpu);
*/
env->msr_mask &= ~(1 << 6);
/* Tell KVM that we're in PAPR mode */
if (kvm_enabled()) {
kvmppc_set_papr(cpu);
}
if (cpu->max_compat) { if (cpu->max_compat) {
Error *local_err = NULL; Error *local_err = NULL;

1
target-ppc/cpu.h
View File

@ -1268,6 +1268,7 @@ void store_booke_tcr (CPUPPCState *env, target_ulong val);
void store_booke_tsr (CPUPPCState *env, target_ulong val); void store_booke_tsr (CPUPPCState *env, target_ulong val);
void ppc_tlb_invalidate_all (CPUPPCState *env); void ppc_tlb_invalidate_all (CPUPPCState *env);
void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr); void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
void cpu_ppc_set_papr(PowerPCCPU *cpu);
#endif #endif
#endif #endif

23
target-ppc/translate_init.c
View File

@ -8380,8 +8380,29 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
pcc->l1_icache_size = 0x8000; pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
} }
#endif /* defined (TARGET_PPC64) */
#if !defined(CONFIG_USER_ONLY)
void cpu_ppc_set_papr(PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
/* PAPR always has exception vectors in RAM not ROM. To ensure this,
* MSR[IP] should never be set.
*
* We also disallow setting of MSR_HV
*/
env->msr_mask &= ~((1ull << MSR_EP) | MSR_HVB);
/* Tell KVM that we're in PAPR mode */
if (kvm_enabled()) {
kvmppc_set_papr(cpu);
}
}
#endif /* !defined(CONFIG_USER_ONLY) */
#endif /* defined (TARGET_PPC64) */
/*****************************************************************************/ /*****************************************************************************/
/* Generic CPU instantiation routine */ /* Generic CPU instantiation routine */