From 268b1b3dfbb92a9348406f728a33f39e3d8dcd8a Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 18 May 2020 15:28:01 +0100 Subject: [PATCH] target/arm: Allow user-mode code to write CPSR.E via MSR Using the MSR instruction to write to CPSR.E is deprecated, but it is required to work from any mode including unprivileged code. We were incorrectly forbidding usermode code from writing it because CPSR_USER did not include the CPSR_E bit. We use CPSR_USER in only three places: * as the mask of what to allow userspace MSR to write to CPSR * when deciding what bits a linux-user signal-return should be able to write from the sigcontext structure * in target_user_copy_regs() when we set up the initial registers for the linux-user process In the first two cases not being able to update CPSR.E is a bug, and in the third case it doesn't matter because CPSR.E is always 0 there. So we can fix both bugs by adding CPSR_E to CPSR_USER. Because the cpsr_write() in restore_sigcontext() is now changing a CPSR bit which is cached in hflags, we need to add an arm_rebuild_hflags() call there; the callsite in target_user_copy_regs() was already rebuilding hflags for other reasons. (The recommended way to change CPSR.E is to use the 'SETEND' instruction, which we do correctly allow from usermode code.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200518142801.20503-1-peter.maydell@linaro.org --- linux-user/arm/signal.c | 1 + target/arm/cpu.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c index d96fc27ce1..8020c80acb 100644 --- a/linux-user/arm/signal.c +++ b/linux-user/arm/signal.c @@ -546,6 +546,7 @@ restore_sigcontext(CPUARMState *env, struct target_sigcontext *sc) #ifdef TARGET_CONFIG_CPU_32 __get_user(cpsr, &sc->arm_cpsr); cpsr_write(env, cpsr, CPSR_USER | CPSR_EXEC, CPSRWriteByInstr); + arm_rebuild_hflags(env); #endif err |= !valid_user_regs(env); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5d995368d4..677584e5da 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1230,7 +1230,7 @@ void pmu_init(ARMCPU *cpu); #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ | CPSR_NZCV) /* Bits writable in user mode. */ -#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) +#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) /* Execution state bits. MRS read as zero, MSR writes ignored. */ #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)