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target/i386: allow instructions with more than one immediate

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While keeping decode->immediate for convenience and for 4-operand instructions,
store the immediate in X86DecodedOp as well.  This enables instructions
with more than one immediate such as ENTER.  It can also be used for far
calls and jumps.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2023-10-23 08:41:39 +02:00
parent 442e38c4fb
commit 2666fbd271
3 changed files with 16 additions and 7 deletions
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2
target/i386/tcg/decode-new.c.inc
View File

@ -1473,7 +1473,7 @@ static bool decode_op(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
case X86_TYPE_I: /* Immediate */ case X86_TYPE_I: /* Immediate */
case X86_TYPE_J: /* Relative offset for a jump */ case X86_TYPE_J: /* Relative offset for a jump */
op->unit = X86_OP_IMM; op->unit = X86_OP_IMM;
decode->immediate = insn_get_signed(env, s, op->ot); decode->immediate = op->imm = insn_get_signed(env, s, op->ot);
break; break;
case X86_TYPE_L: /* The upper 4 bits of the immediate select a 128-bit register */ case X86_TYPE_L: /* The upper 4 bits of the immediate select a 128-bit register */

17
target/i386/tcg/decode-new.h
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@ -271,16 +271,23 @@ typedef struct X86DecodedOp {
bool has_ea; bool has_ea;
int offset; /* For MMX and SSE */ int offset; /* For MMX and SSE */
/* union {
* This field is used internally by macros OP0_PTR/OP1_PTR/OP2_PTR, target_ulong imm;
* do not access directly! /*
*/ * This field is used internally by macros OP0_PTR/OP1_PTR/OP2_PTR,
TCGv_ptr v_ptr; * do not access directly!
*/
TCGv_ptr v_ptr;
};
} X86DecodedOp; } X86DecodedOp;
struct X86DecodedInsn { struct X86DecodedInsn {
X86OpEntry e; X86OpEntry e;
X86DecodedOp op[3]; X86DecodedOp op[3];
/*
* Rightmost immediate, for convenience since most instructions have
* one (and also for 4-operand instructions).
*/
target_ulong immediate; target_ulong immediate;
AddressParts mem; AddressParts mem;

4
target/i386/tcg/emit.c.inc
View File

@ -259,7 +259,7 @@ static void gen_load(DisasContext *s, X86DecodedInsn *decode, int opn, TCGv v)
} }
break; break;
case X86_OP_IMM: case X86_OP_IMM:
tcg_gen_movi_tl(v, decode->immediate); tcg_gen_movi_tl(v, op->imm);
break; break;
case X86_OP_MMX: case X86_OP_MMX:
@ -283,6 +283,8 @@ static void gen_load(DisasContext *s, X86DecodedInsn *decode, int opn, TCGv v)
static TCGv_ptr op_ptr(X86DecodedInsn *decode, int opn) static TCGv_ptr op_ptr(X86DecodedInsn *decode, int opn)
{ {
X86DecodedOp *op = &decode->op[opn]; X86DecodedOp *op = &decode->op[opn];
assert(op->unit == X86_OP_MMX || op->unit == X86_OP_SSE);
if (op->v_ptr) { if (op->v_ptr) {
return op->v_ptr; return op->v_ptr;
} }