Hexagon (target/hexagon) Clean up pred_written usage
Only endloop instructions will conditionally write to a predicate. When there is an endloop instruction, we preload the values into new_pred_value. The only place pred_written is needed is when HEX_DEBUG is on. We remove the last use of check_for_attrib. However, new uses will be introduced later in this series, so we mark it with G_GNUC_UNUSED. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-9-tsimpson@quicinc.com>
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@ -137,7 +137,9 @@ void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val)
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tcg_gen_and_tl(hex_new_pred_value[pnum],
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hex_new_pred_value[pnum], base_val);
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}
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if (HEX_DEBUG) {
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tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << pnum);
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}
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set_bit(pnum, ctx->pregs_written);
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}
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@ -826,15 +828,13 @@ static void gen_endloop0(DisasContext *ctx)
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/*
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* if (lpcfg == 1) {
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* hex_new_pred_value[3] = 0xff;
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* hex_pred_written |= 1 << 3;
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* p3 = 0xff;
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* }
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*/
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TCGLabel *label1 = gen_new_label();
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tcg_gen_brcondi_tl(TCG_COND_NE, lpcfg, 1, label1);
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{
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tcg_gen_movi_tl(hex_new_pred_value[3], 0xff);
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tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << 3);
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gen_log_pred_write(ctx, 3, tcg_constant_tl(0xff));
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}
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gen_set_label(label1);
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@ -903,14 +903,12 @@ static void gen_endloop01(DisasContext *ctx)
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/*
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* if (lpcfg == 1) {
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* hex_new_pred_value[3] = 0xff;
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* hex_pred_written |= 1 << 3;
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* p3 = 0xff;
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* }
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*/
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tcg_gen_brcondi_tl(TCG_COND_NE, lpcfg, 1, label1);
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{
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tcg_gen_movi_tl(hex_new_pred_value[3], 0xff);
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tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << 3);
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gen_log_pred_write(ctx, 3, tcg_constant_tl(0xff));
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}
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gen_set_label(label1);
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@ -239,7 +239,7 @@ static int read_packet_words(CPUHexagonState *env, DisasContext *ctx,
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return nwords;
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}
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static bool check_for_attrib(Packet *pkt, int attrib)
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static G_GNUC_UNUSED bool check_for_attrib(Packet *pkt, int attrib)
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{
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for (int i = 0; i < pkt->num_insns; i++) {
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if (GET_ATTRIB(pkt->insn[i].opcode, attrib)) {
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@ -262,11 +262,6 @@ static bool need_slot_cancelled(Packet *pkt)
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return false;
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}
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static bool need_pred_written(Packet *pkt)
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{
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return check_for_attrib(pkt, A_WRITES_PRED_REG);
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}
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static bool need_next_PC(DisasContext *ctx)
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{
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Packet *pkt = ctx->pkt;
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@ -414,7 +409,7 @@ static void gen_start_packet(DisasContext *ctx)
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tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], next_PC);
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}
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}
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if (need_pred_written(pkt)) {
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if (HEX_DEBUG) {
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tcg_gen_movi_tl(hex_pred_written, 0);
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}
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@ -428,6 +423,17 @@ static void gen_start_packet(DisasContext *ctx)
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}
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}
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/*
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* Preload the predicated pred registers into hex_new_pred_value[pred_num]
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* Only endloop instructions conditionally write to pred registers
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*/
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if (pkt->pkt_has_endloop) {
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for (int i = 0; i < ctx->preg_log_idx; i++) {
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int pred_num = ctx->preg_log[i];
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tcg_gen_mov_tl(hex_new_pred_value[pred_num], hex_pred[pred_num]);
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}
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}
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/* Preload the predicated HVX registers into future_VRegs and tmp_VRegs */
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if (!bitmap_empty(ctx->predicated_future_vregs, NUM_VREGS)) {
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int i = find_first_bit(ctx->predicated_future_vregs, NUM_VREGS);
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@ -535,41 +541,14 @@ static void gen_reg_writes(DisasContext *ctx)
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static void gen_pred_writes(DisasContext *ctx)
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{
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int i;
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/* Early exit if the log is empty */
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if (!ctx->preg_log_idx) {
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return;
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}
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/*
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* Only endloop instructions will conditionally
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* write a predicate. If there are no endloop
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* instructions, we can use the non-conditional
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* write of the predicates.
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*/
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if (ctx->pkt->pkt_has_endloop) {
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TCGv zero = tcg_constant_tl(0);
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TCGv pred_written = tcg_temp_new();
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for (i = 0; i < ctx->preg_log_idx; i++) {
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int pred_num = ctx->preg_log[i];
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tcg_gen_andi_tl(pred_written, hex_pred_written, 1 << pred_num);
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tcg_gen_movcond_tl(TCG_COND_NE, hex_pred[pred_num],
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pred_written, zero,
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hex_new_pred_value[pred_num],
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hex_pred[pred_num]);
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}
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} else {
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for (i = 0; i < ctx->preg_log_idx; i++) {
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for (int i = 0; i < ctx->preg_log_idx; i++) {
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int pred_num = ctx->preg_log[i];
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tcg_gen_mov_tl(hex_pred[pred_num], hex_new_pred_value[pred_num]);
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if (HEX_DEBUG) {
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/* Do this so HELPER(debug_commit_end) will know */
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tcg_gen_ori_tl(hex_pred_written, hex_pred_written,
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1 << pred_num);
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}
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}
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}
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}
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