tests/tcg/s390x: Test CLC with inaccessible second operand
Add a small test to prevent regressions.
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20231106093605.1349201-3-iii@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
(cherry picked from commit 43fecbe7a5
)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
This commit is contained in:
parent
88b778e4c2
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@ -41,6 +41,7 @@ TESTS+=larl
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TESTS+=mdeb
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TESTS+=cgebra
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TESTS+=clgebr
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TESTS+=clc
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cdsg: CFLAGS+=-pthread
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cdsg: LDFLAGS+=-pthread
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48
tests/tcg/s390x/clc.c
Normal file
48
tests/tcg/s390x/clc.c
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@ -0,0 +1,48 @@
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/*
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* Test the CLC instruction.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include <assert.h>
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#include <signal.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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static void handle_sigsegv(int sig, siginfo_t *info, void *ucontext)
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{
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mcontext_t *mcontext = &((ucontext_t *)ucontext)->uc_mcontext;
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if (mcontext->gregs[0] != 600) {
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write(STDERR_FILENO, "bad r0\n", 7);
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_exit(EXIT_FAILURE);
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}
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if (((mcontext->psw.mask >> 44) & 3) != 1) {
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write(STDERR_FILENO, "bad cc\n", 7);
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_exit(EXIT_FAILURE);
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}
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_exit(EXIT_SUCCESS);
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}
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int main(void)
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{
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register unsigned long r0 asm("r0");
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unsigned long mem = 42, rhs = 500;
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struct sigaction act;
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int err;
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memset(&act, 0, sizeof(act));
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act.sa_sigaction = handle_sigsegv;
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act.sa_flags = SA_SIGINFO;
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err = sigaction(SIGSEGV, &act, NULL);
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assert(err == 0);
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r0 = 100;
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asm("algr %[r0],%[rhs]\n"
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"clc 0(8,%[mem]),0(0)\n" /* The 2nd operand will cause a SEGV. */
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: [r0] "+r" (r0)
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: [mem] "r" (&mem)
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, [rhs] "r" (rhs)
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: "cc", "memory");
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return EXIT_FAILURE;
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}
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