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tcg/loongarch64: Lower vector bitwise operations

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Lower the following ops:

- and_vec
- andc_vec
- or_vec
- orc_vec
- xor_vec
- nor_vec
- not_vec

Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230908022302.180442-7-c@jia.je>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Jiajie Chen 2023-09-08 10:21:13 +08:00 committed by Richard Henderson
parent e9d7c8cf95
commit 24c42fde52
3 changed files with 50 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
tcg/loongarch64/tcg-target-con-set.h
View File

@ -20,6 +20,7 @@ C_O0_I2(rZ, rZ)
C_O0_I2(w, r)
C_O1_I1(r, r)
C_O1_I1(w, r)
C_O1_I1(w, w)
C_O1_I2(r, r, rC)
C_O1_I2(r, r, ri)
C_O1_I2(r, r, rI)
@ -31,6 +32,7 @@ C_O1_I2(r, 0, rZ)
C_O1_I2(r, rZ, ri)
C_O1_I2(r, rZ, rJ)
C_O1_I2(r, rZ, rZ)
C_O1_I2(w, w, w)
C_O1_I2(w, w, wM)
C_O1_I2(w, w, wA)
C_O1_I4(r, rZ, rJ, rZ, rZ)

44
tcg/loongarch64/tcg-target.c.inc
View File

@ -1722,6 +1722,32 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out_opc_vldx(s, a0, a1, temp);
}
break;
case INDEX_op_and_vec:
tcg_out_opc_vand_v(s, a0, a1, a2);
break;
case INDEX_op_andc_vec:
/*
* vandn vd, vj, vk: vd = vk & ~vj
* andc_vec vd, vj, vk: vd = vj & ~vk
* vk and vk are swapped
*/
tcg_out_opc_vandn_v(s, a0, a2, a1);
break;
case INDEX_op_or_vec:
tcg_out_opc_vor_v(s, a0, a1, a2);
break;
case INDEX_op_orc_vec:
tcg_out_opc_vorn_v(s, a0, a1, a2);
break;
case INDEX_op_xor_vec:
tcg_out_opc_vxor_v(s, a0, a1, a2);
break;
case INDEX_op_nor_vec:
tcg_out_opc_vnor_v(s, a0, a1, a2);
break;
case INDEX_op_not_vec:
tcg_out_opc_vnor_v(s, a0, a1, a1);
break;
case INDEX_op_cmp_vec:
TCGCond cond = args[3];
if (const_args[2]) {
@ -1785,6 +1811,13 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_cmp_vec:
case INDEX_op_add_vec:
case INDEX_op_sub_vec:
case INDEX_op_and_vec:
case INDEX_op_andc_vec:
case INDEX_op_or_vec:
case INDEX_op_orc_vec:
case INDEX_op_xor_vec:
case INDEX_op_nor_vec:
case INDEX_op_not_vec:
return 1;
default:
return 0;
@ -1953,6 +1986,17 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_sub_vec:
return C_O1_I2(w, w, wA);
case INDEX_op_and_vec:
case INDEX_op_andc_vec:
case INDEX_op_or_vec:
case INDEX_op_orc_vec:
case INDEX_op_xor_vec:
case INDEX_op_nor_vec:
return C_O1_I2(w, w, w);
case INDEX_op_not_vec:
return C_O1_I1(w, w);
default:
g_assert_not_reached();
}

8
tcg/loongarch64/tcg-target.h
View File

@ -177,13 +177,13 @@ extern bool use_lsx_instructions;
#define TCG_TARGET_HAS_v128 use_lsx_instructions
#define TCG_TARGET_HAS_v256 0
#define TCG_TARGET_HAS_not_vec 0
#define TCG_TARGET_HAS_not_vec 1
#define TCG_TARGET_HAS_neg_vec 0
#define TCG_TARGET_HAS_abs_vec 0
#define TCG_TARGET_HAS_andc_vec 0
#define TCG_TARGET_HAS_orc_vec 0
#define TCG_TARGET_HAS_andc_vec 1
#define TCG_TARGET_HAS_orc_vec 1
#define TCG_TARGET_HAS_nand_vec 0
#define TCG_TARGET_HAS_nor_vec 0
#define TCG_TARGET_HAS_nor_vec 1
#define TCG_TARGET_HAS_eqv_vec 0
#define TCG_TARGET_HAS_mul_vec 0
#define TCG_TARGET_HAS_shi_vec 0