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hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI)

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This patch realize PCH-MSI interrupt controller.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-34-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Xiaojuan Yang 2022-06-06 20:43:23 +08:00 committed by Richard Henderson
parent 0f4fcf1845
commit 249ad85a4b
7 changed files with 106 additions and 0 deletions
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5
hw/intc/Kconfig
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@ -94,3 +94,8 @@ config LOONGARCH_IPI
config LOONGARCH_PCH_PIC
bool
select UNIMP
config LOONGARCH_PCH_MSI
select MSI_NONBROKEN
bool
select UNIMP

73
hw/intc/loongarch_pch_msi.c Normal file
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@ -0,0 +1,73 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* QEMU Loongson 7A1000 msi interrupt controller.
*
* Copyright (C) 2021 Loongson Technology Corporation Limited
*/
#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "hw/irq.h"
#include "hw/intc/loongarch_pch_msi.h"
#include "hw/intc/loongarch_pch_pic.h"
#include "hw/pci/msi.h"
#include "hw/misc/unimp.h"
#include "migration/vmstate.h"
#include "trace.h"
static uint64_t loongarch_msi_mem_read(void *opaque, hwaddr addr, unsigned size)
{
return 0;
}
static void loongarch_msi_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(opaque);
int irq_num = val & 0xff;
trace_loongarch_msi_set_irq(irq_num);
assert(irq_num < PCH_MSI_IRQ_NUM);
qemu_set_irq(s->pch_msi_irq[irq_num], 1);
}
static const MemoryRegionOps loongarch_pch_msi_ops = {
.read = loongarch_msi_mem_read,
.write = loongarch_msi_mem_write,
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void pch_msi_irq_handler(void *opaque, int irq, int level)
{
LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(opaque);
qemu_set_irq(s->pch_msi_irq[irq], level);
}
static void loongarch_pch_msi_init(Object *obj)
{
LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
memory_region_init_io(&s->msi_mmio, obj, &loongarch_pch_msi_ops,
s, TYPE_LOONGARCH_PCH_MSI, 0x8);
sysbus_init_mmio(sbd, &s->msi_mmio);
msi_nonbroken = true;
qdev_init_gpio_out(DEVICE(obj), s->pch_msi_irq, PCH_MSI_IRQ_NUM);
qdev_init_gpio_in(DEVICE(obj), pch_msi_irq_handler, PCH_MSI_IRQ_NUM);
}
static const TypeInfo loongarch_pch_msi_info = {
.name = TYPE_LOONGARCH_PCH_MSI,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(LoongArchPCHMSI),
.instance_init = loongarch_pch_msi_init,
};
static void loongarch_pch_msi_register_types(void)
{
type_register_static(&loongarch_pch_msi_info);
}
type_init(loongarch_pch_msi_register_types)

1
hw/intc/meson.build
View File

@ -65,3 +65,4 @@ specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
specific_ss.add(when: 'CONFIG_NIOS2_VIC', if_true: files('nios2_vic.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ipi.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_msi.c'))

3
hw/intc/trace-events
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@ -300,3 +300,6 @@ loongarch_pch_pic_high_readw(unsigned size, uint64_t addr, uint64_t val) "size:
loongarch_pch_pic_high_writew(unsigned size, uint64_t addr, uint64_t val) "size: %u addr: 0x%"PRIx64 "val: 0x%" PRIx64
loongarch_pch_pic_readb(unsigned size, uint64_t addr, uint64_t val) "size: %u addr: 0x%"PRIx64 "val: 0x%" PRIx64
loongarch_pch_pic_writeb(unsigned size, uint64_t addr, uint64_t val) "size: %u addr: 0x%"PRIx64 "val: 0x%" PRIx64
# loongarch_pch_msi.c
loongarch_msi_set_irq(int irq_num) "set msi irq %d"

1
hw/loongarch/Kconfig
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@ -4,3 +4,4 @@ config LOONGARCH_VIRT
select PCI_EXPRESS_GENERIC_BRIDGE
select LOONGARCH_IPI
select LOONGARCH_PCH_PIC
select LOONGARCH_PCH_MSI

20
include/hw/intc/loongarch_pch_msi.h Normal file
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@ -0,0 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* LoongArch 7A1000 I/O interrupt controller definitions
*
* Copyright (C) 2021 Loongson Technology Corporation Limited
*/
#define TYPE_LOONGARCH_PCH_MSI "loongarch_pch_msi"
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHMSI, LOONGARCH_PCH_MSI)
/* Msi irq start start from 64 to 255 */
#define PCH_MSI_IRQ_START 64
#define PCH_MSI_IRQ_END 255
#define PCH_MSI_IRQ_NUM 192
struct LoongArchPCHMSI {
SysBusDevice parent_obj;
qemu_irq pch_msi_irq[PCH_MSI_IRQ_NUM];
MemoryRegion msi_mmio;
};

3
include/hw/pci-host/ls7a.h
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@ -15,6 +15,9 @@
#include "qemu/range.h"
#include "qom/object.h"
#define LS7A_PCI_MEM_BASE 0x40000000UL
#define LS7A_PCI_MEM_SIZE 0x40000000UL
#define LS7A_PCH_REG_BASE 0x10000000UL
#define LS7A_IOAPIC_REG_BASE (LS7A_PCH_REG_BASE)
#define LS7A_PCH_MSI_ADDR_LOW 0x2FF00000UL