From 24299c892cbfe29120f051b6b7d0bcf3e0cc8e85 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Llu=C3=ADs=20Vilanova?= Date: Fri, 14 Jul 2017 12:38:21 +0300 Subject: [PATCH] target/arm: [tcg,a64] Port to translate_insn MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Incrementally paves the way towards using the generic instruction translation loop. Reviewed-by: Emilio G. Cota Signed-off-by: Lluís Vilanova Message-Id: <150002510079.22386.10164419868911710218.stgit@frigg.lan> [rth: Adjust for translate_insn interface change.] Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 71 +++++++++++++++++++++++--------------- 1 file changed, 43 insertions(+), 28 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e94198280d..f959f4469a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11254,6 +11254,9 @@ static int aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->is_ldex = false; dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el); + dc->next_page_start = + (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; + init_tmp_a64_array(dc); return max_insns; @@ -11291,12 +11294,43 @@ static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, return true; } +static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + CPUARMState *env = cpu->env_ptr; + + if (dc->ss_active && !dc->pstate_ss) { + /* Singlestep state is Active-pending. + * If we're in this state at the start of a TB then either + * a) we just took an exception to an EL which is being debugged + * and this is the first insn in the exception handler + * b) debug exceptions were masked and we just unmasked them + * without changing EL (eg by clearing PSTATE.D) + * In either case we're going to take a swstep exception in the + * "did not step an insn" case, and so the syndrome ISV and EX + * bits should be zero. + */ + assert(dc->base.num_insns == 1); + gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), + default_exception_el(dc)); + dc->base.is_jmp = DISAS_NORETURN; + } else { + disas_a64_insn(env, dc); + } + + if (dc->base.is_jmp == DISAS_NEXT) { + if (dc->ss_active || dc->pc >= dc->next_page_start) { + dc->base.is_jmp = DISAS_TOO_MANY; + } + } + + dc->base.pc_next = dc->pc; +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { - CPUARMState *env = cs->env_ptr; DisasContext *dc = container_of(dcbase, DisasContext, base); - target_ulong next_page_start; int max_insns; dc->base.tb = tb; @@ -11306,7 +11340,6 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, dc->base.num_insns = 0; dc->base.singlestep_enabled = cs->singlestep_enabled; - next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; max_insns = dc->base.tb->cflags & CF_COUNT_MASK; if (max_insns == 0) { max_insns = CF_COUNT_MASK; @@ -11342,42 +11375,24 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, gen_io_start(); } - if (dc->ss_active && !dc->pstate_ss) { - /* Singlestep state is Active-pending. - * If we're in this state at the start of a TB then either - * a) we just took an exception to an EL which is being debugged - * and this is the first insn in the exception handler - * b) debug exceptions were masked and we just unmasked them - * without changing EL (eg by clearing PSTATE.D) - * In either case we're going to take a swstep exception in the - * "did not step an insn" case, and so the syndrome ISV and EX - * bits should be zero. - */ - assert(dc->base.num_insns == 1); - gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), - default_exception_el(dc)); - dc->base.is_jmp = DISAS_NORETURN; - break; - } - - disas_a64_insn(env, dc); + aarch64_tr_translate_insn(&dc->base, cs); if (tcg_check_temp_count()) { fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", dc->pc); } + if (!dc->base.is_jmp && (tcg_op_buf_full() || cs->singlestep_enabled || + singlestep || dc->base.num_insns >= max_insns)) { + dc->base.is_jmp = DISAS_TOO_MANY; + } + /* Translation stops when a conditional branch is encountered. * Otherwise the subsequent code could get translated several times. * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ - } while (!dc->base.is_jmp && !tcg_op_buf_full() && - !cs->singlestep_enabled && - !singlestep && - !dc->ss_active && - dc->pc < next_page_start && - dc->base.num_insns < max_insns); + } while (!dc->base.is_jmp); if (dc->base.tb->cflags & CF_LAST_IO) { gen_io_end();