target/arm: Factor out PMU register definitions
Pull the code that defines the various PMU registers out into its own function, matching the pattern we have already for the debug registers. Apart from one style fix to a multi-line comment, this is purely movement of code with no changes to it. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200214175116.9164-6-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
22e570730d
commit
24183fb6f0
@ -6317,6 +6317,87 @@ static void define_debug_regs(ARMCPU *cpu)
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}
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}
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static void define_pmu_regs(ARMCPU *cpu)
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{
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/*
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* v7 performance monitor control register: same implementor
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* field as main ID register, and we implement four counters in
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* addition to the cycle count register.
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*/
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unsigned int i, pmcrn = 4;
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ARMCPRegInfo pmcr = {
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.name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
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.access = PL0_RW,
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.type = ARM_CP_IO | ARM_CP_ALIAS,
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.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
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.accessfn = pmreg_access, .writefn = pmcr_write,
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.raw_writefn = raw_write,
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};
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ARMCPRegInfo pmcr64 = {
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.name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
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.access = PL0_RW, .accessfn = pmreg_access,
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.type = ARM_CP_IO,
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
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.resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT),
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.writefn = pmcr_write, .raw_writefn = raw_write,
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};
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define_one_arm_cp_reg(cpu, &pmcr);
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define_one_arm_cp_reg(cpu, &pmcr64);
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for (i = 0; i < pmcrn; i++) {
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char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i);
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char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i);
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char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i);
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char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i);
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ARMCPRegInfo pmev_regs[] = {
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{ .name = pmevcntr_name, .cp = 15, .crn = 14,
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.crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
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.access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
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.readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
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.accessfn = pmreg_access },
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{ .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),
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.opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
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.type = ARM_CP_IO,
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.readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
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.raw_readfn = pmevcntr_rawread,
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.raw_writefn = pmevcntr_rawwrite },
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{ .name = pmevtyper_name, .cp = 15, .crn = 14,
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.crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
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.access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
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.readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
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.accessfn = pmreg_access },
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{ .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)),
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.opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
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.type = ARM_CP_IO,
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.readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
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.raw_writefn = pmevtyper_rawwrite },
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REGINFO_SENTINEL
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};
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define_arm_cp_regs(cpu, pmev_regs);
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g_free(pmevcntr_name);
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g_free(pmevcntr_el0_name);
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g_free(pmevtyper_name);
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g_free(pmevtyper_el0_name);
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}
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if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
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FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) != 0xf) {
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ARMCPRegInfo v81_pmu_regs[] = {
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{ .name = "PMCEID2", .state = ARM_CP_STATE_AA32,
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.cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4,
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.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
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.resetvalue = extract64(cpu->pmceid0, 32, 32) },
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{ .name = "PMCEID3", .state = ARM_CP_STATE_AA32,
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.cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,
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.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
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.resetvalue = extract64(cpu->pmceid1, 32, 32) },
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REGINFO_SENTINEL
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};
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define_arm_cp_regs(cpu, v81_pmu_regs);
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}
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}
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/* We don't know until after realize whether there's a GICv3
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* attached, and that is what registers the gicv3 sysregs.
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* So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
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@ -6859,67 +6940,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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define_arm_cp_regs(cpu, pmovsset_cp_reginfo);
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}
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if (arm_feature(env, ARM_FEATURE_V7)) {
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/* v7 performance monitor control register: same implementor
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* field as main ID register, and we implement four counters in
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* addition to the cycle count register.
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*/
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unsigned int i, pmcrn = 4;
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ARMCPRegInfo pmcr = {
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.name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
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.access = PL0_RW,
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.type = ARM_CP_IO | ARM_CP_ALIAS,
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.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
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.accessfn = pmreg_access, .writefn = pmcr_write,
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.raw_writefn = raw_write,
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};
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ARMCPRegInfo pmcr64 = {
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.name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
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.access = PL0_RW, .accessfn = pmreg_access,
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.type = ARM_CP_IO,
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
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.resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT),
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.writefn = pmcr_write, .raw_writefn = raw_write,
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};
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define_one_arm_cp_reg(cpu, &pmcr);
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define_one_arm_cp_reg(cpu, &pmcr64);
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for (i = 0; i < pmcrn; i++) {
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char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i);
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char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i);
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char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i);
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char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i);
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ARMCPRegInfo pmev_regs[] = {
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{ .name = pmevcntr_name, .cp = 15, .crn = 14,
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.crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
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.access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
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.readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
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.accessfn = pmreg_access },
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{ .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),
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.opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
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.type = ARM_CP_IO,
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.readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
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.raw_readfn = pmevcntr_rawread,
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.raw_writefn = pmevcntr_rawwrite },
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{ .name = pmevtyper_name, .cp = 15, .crn = 14,
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.crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
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.access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
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.readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
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.accessfn = pmreg_access },
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{ .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)),
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.opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
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.type = ARM_CP_IO,
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.readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
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.raw_writefn = pmevtyper_rawwrite },
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REGINFO_SENTINEL
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};
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define_arm_cp_regs(cpu, pmev_regs);
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g_free(pmevcntr_name);
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g_free(pmevcntr_el0_name);
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g_free(pmevtyper_name);
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g_free(pmevtyper_el0_name);
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}
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ARMCPRegInfo clidr = {
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.name = "CLIDR", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
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@ -6930,24 +6950,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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define_one_arm_cp_reg(cpu, &clidr);
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define_arm_cp_regs(cpu, v7_cp_reginfo);
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define_debug_regs(cpu);
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define_pmu_regs(cpu);
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} else {
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define_arm_cp_regs(cpu, not_v7_cp_reginfo);
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}
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if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
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FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) != 0xf) {
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ARMCPRegInfo v81_pmu_regs[] = {
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{ .name = "PMCEID2", .state = ARM_CP_STATE_AA32,
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.cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4,
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.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
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.resetvalue = extract64(cpu->pmceid0, 32, 32) },
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{ .name = "PMCEID3", .state = ARM_CP_STATE_AA32,
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.cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,
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.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
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.resetvalue = extract64(cpu->pmceid1, 32, 32) },
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REGINFO_SENTINEL
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};
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define_arm_cp_regs(cpu, v81_pmu_regs);
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}
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if (arm_feature(env, ARM_FEATURE_V8)) {
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/* AArch64 ID registers, which all have impdef reset values.
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* Note that within the ID register ranges the unused slots
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