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target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns

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Vector widening conversion instructions are provided to and from all
supported integer EEWs for Zve64f extension.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-9-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang 2022-01-18 09:45:11 +08:00 committed by Alistair Francis
parent 193fb5c9bd
commit 235d1161d4
1 changed files with 25 additions and 7 deletions
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32
target/riscv/insn_trans/trans_rvv.c.inc
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@ -77,6 +77,17 @@ static bool require_zve64f(DisasContext *s)
return s->ext_zve64f ? s->sew <= MO_32 : true; return s->ext_zve64f ? s->sew <= MO_32 : true;
} }
static bool require_scale_zve64f(DisasContext *s)
{
/* RVV + Zve64f = RVV. */
if (has_ext(s, RVV)) {
return true;
}
/* Zve64f doesn't support FP64. (Section 18.2) */
return s->ext_zve64f ? s->sew <= MO_16 : true;
}
/* Destination vector register group cannot overlap source mask register. */ /* Destination vector register group cannot overlap source mask register. */
static bool require_vm(int vm, int vd) static bool require_vm(int vm, int vd)
{ {
@ -2333,7 +2344,8 @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
require_scale_rvf(s) && require_scale_rvf(s) &&
(s->sew != MO_8) && (s->sew != MO_8) &&
vext_check_isa_ill(s) && vext_check_isa_ill(s) &&
vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm); vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
require_scale_zve64f(s);
} }
/* OPFVV with WIDEN */ /* OPFVV with WIDEN */
@ -2372,7 +2384,8 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
require_scale_rvf(s) && require_scale_rvf(s) &&
(s->sew != MO_8) && (s->sew != MO_8) &&
vext_check_isa_ill(s) && vext_check_isa_ill(s) &&
vext_check_ds(s, a->rd, a->rs2, a->vm); vext_check_ds(s, a->rd, a->rs2, a->vm) &&
require_scale_zve64f(s);
} }
/* OPFVF with WIDEN */ /* OPFVF with WIDEN */
@ -2402,7 +2415,8 @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
require_scale_rvf(s) && require_scale_rvf(s) &&
(s->sew != MO_8) && (s->sew != MO_8) &&
vext_check_isa_ill(s) && vext_check_isa_ill(s) &&
vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm); vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm) &&
require_scale_zve64f(s);
} }
/* WIDEN OPFVV with WIDEN */ /* WIDEN OPFVV with WIDEN */
@ -2441,7 +2455,8 @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
require_scale_rvf(s) && require_scale_rvf(s) &&
(s->sew != MO_8) && (s->sew != MO_8) &&
vext_check_isa_ill(s) && vext_check_isa_ill(s) &&
vext_check_dd(s, a->rd, a->rs2, a->vm); vext_check_dd(s, a->rd, a->rs2, a->vm) &&
require_scale_zve64f(s);
} }
/* WIDEN OPFVF with WIDEN */ /* WIDEN OPFVF with WIDEN */
@ -2700,14 +2715,16 @@ static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
static bool opxfv_widen_check(DisasContext *s, arg_rmr *a) static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
{ {
return opfv_widen_check(s, a) && return opfv_widen_check(s, a) &&
require_rvf(s); require_rvf(s) &&
require_zve64f(s);
} }
static bool opffv_widen_check(DisasContext *s, arg_rmr *a) static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
{ {
return opfv_widen_check(s, a) && return opfv_widen_check(s, a) &&
require_scale_rvf(s) && require_scale_rvf(s) &&
(s->sew != MO_8); (s->sew != MO_8) &&
require_scale_zve64f(s);
} }
#define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM) \ #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM) \
@ -2758,7 +2775,8 @@ static bool opfxv_widen_check(DisasContext *s, arg_rmr *a)
require_scale_rvf(s) && require_scale_rvf(s) &&
vext_check_isa_ill(s) && vext_check_isa_ill(s) &&
/* OPFV widening instructions ignore vs1 check */ /* OPFV widening instructions ignore vs1 check */
vext_check_ds(s, a->rd, a->rs2, a->vm); vext_check_ds(s, a->rd, a->rs2, a->vm) &&
require_scale_zve64f(s);
} }
#define GEN_OPFXV_WIDEN_TRANS(NAME) \ #define GEN_OPFXV_WIDEN_TRANS(NAME) \