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hw/arm/armsse: Add unimplemented-device stub for cache control registers

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The SSE-200 gives each CPU a register bank to use to control its
L1 instruction cache. Put in an unimplemented-device stub for this.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190121185118.18550-18-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2019-02-01 14:55:43 +00:00
parent e0b00f1b92
commit 2357bca532
2 changed files with 39 additions and 1 deletions
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39
hw/arm/armsse.c
View File

@ -32,6 +32,7 @@ struct ARMSSEInfo {
SysConfigFormat sys_config_format;
bool has_mhus;
bool has_ppus;
bool has_cachectrl;
};
static const ARMSSEInfo armsse_variants[] = {
@ -43,6 +44,7 @@ static const ARMSSEInfo armsse_variants[] = {
.sys_config_format = IoTKitFormat,
.has_mhus = false,
.has_ppus = false,
.has_cachectrl = false,
},
};
@ -290,6 +292,16 @@ static void armsse_init(Object *obj)
g_free(name);
}
}
if (info->has_cachectrl) {
for (i = 0; i < info->num_cpus; i++) {
char *name = g_strdup_printf("cachectrl%d", i);
sysbus_init_child_obj(obj, name, &s->cachectrl[i],
sizeof(s->cachectrl[i]),
TYPE_UNIMPLEMENTED_DEVICE);
g_free(name);
}
}
object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate,
sizeof(s->nmi_orgate), TYPE_OR_IRQ,
&error_abort, NULL);
@ -795,7 +807,32 @@ static void armsse_realize(DeviceState *dev, Error **errp)
qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0,
armsse_get_common_irq_in(s, 10));
/* 0x40010000 .. 0x4001ffff: private CPU region: unused in IoTKit */
/*
* 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias):
* private per-CPU region (all these devices are SSE-200 only):
* 0x50010000: L1 icache control registers
* 0x50011000: CPUSECCTRL (CPU local security control registers)
* 0x4001f000 and 0x5001f000: CPU_IDENTITY register block
*/
if (info->has_cachectrl) {
for (i = 0; i < info->num_cpus; i++) {
char *name = g_strdup_printf("cachectrl%d", i);
MemoryRegion *mr;
qdev_prop_set_string(DEVICE(&s->cachectrl[i]), "name", name);
g_free(name);
qdev_prop_set_uint64(DEVICE(&s->cachectrl[i]), "size", 0x1000);
object_property_set_bool(OBJECT(&s->cachectrl[i]), true,
"realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cachectrl[i]), 0);
memory_region_add_subregion(&s->cpu_container[i], 0x50010000, mr);
}
}
/* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region */
/* Devices behind APB PPC1:

1
include/hw/arm/armsse.h
View File

@ -150,6 +150,7 @@ typedef struct ARMSSE {
UnimplementedDeviceState mhu[2];
UnimplementedDeviceState ppu[NUM_PPUS];
UnimplementedDeviceState cachectrl[SSE_MAX_CPUS];
/*
* 'container' holds all devices seen by all CPUs.