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target/riscv: csr: Remove redundant check in fp csr read/write routines

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The following check:

    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
        return -RISCV_EXCP_ILLEGAL_INST;
    }

is redundant in fflags/frm/fcsr read/write routines, as the check was
already done in fs().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210627120604.11116-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Bin Meng 2021-06-27 20:06:04 +08:00 committed by Alistair Francis
parent b4cb178efb
commit 232a2c8c85
1 changed files with 0 additions and 24 deletions
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24
target/riscv/csr.c
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@ -215,11 +215,6 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
static RISCVException read_fflags(CPURISCVState *env, int csrno, static RISCVException read_fflags(CPURISCVState *env, int csrno,
target_ulong *val) target_ulong *val)
{ {
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
}
#endif
*val = riscv_cpu_get_fflags(env); *val = riscv_cpu_get_fflags(env);
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
} }
@ -228,9 +223,6 @@ static RISCVException write_fflags(CPURISCVState *env, int csrno,
target_ulong val) target_ulong val)
{ {
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
}
env->mstatus |= MSTATUS_FS; env->mstatus |= MSTATUS_FS;
#endif #endif
riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
@ -240,11 +232,6 @@ static RISCVException write_fflags(CPURISCVState *env, int csrno,
static RISCVException read_frm(CPURISCVState *env, int csrno, static RISCVException read_frm(CPURISCVState *env, int csrno,
target_ulong *val) target_ulong *val)
{ {
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
}
#endif
*val = env->frm; *val = env->frm;
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
} }
@ -253,9 +240,6 @@ static RISCVException write_frm(CPURISCVState *env, int csrno,
target_ulong val) target_ulong val)
{ {
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
}
env->mstatus |= MSTATUS_FS; env->mstatus |= MSTATUS_FS;
#endif #endif
env->frm = val & (FSR_RD >> FSR_RD_SHIFT); env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
@ -265,11 +249,6 @@ static RISCVException write_frm(CPURISCVState *env, int csrno,
static RISCVException read_fcsr(CPURISCVState *env, int csrno, static RISCVException read_fcsr(CPURISCVState *env, int csrno,
target_ulong *val) target_ulong *val)
{ {
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
}
#endif
*val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
| (env->frm << FSR_RD_SHIFT); | (env->frm << FSR_RD_SHIFT);
if (vs(env, csrno) >= 0) { if (vs(env, csrno) >= 0) {
@ -283,9 +262,6 @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno,
target_ulong val) target_ulong val)
{ {
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
}
env->mstatus |= MSTATUS_FS; env->mstatus |= MSTATUS_FS;
#endif #endif
env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;