qga/vss-win32: require widl/midl, remove pre-built TLB file

There are no good reason anymore to keep a pre-built file in the repository.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Marc-André Lureau 2022-02-01 12:55:21 +04:00 committed by Paolo Bonzini
parent 1e1223249d
commit 23011f44d7
4 changed files with 7 additions and 8 deletions

View File

@ -307,8 +307,12 @@ iokit = []
emulator_link_args = [] emulator_link_args = []
nvmm =not_found nvmm =not_found
hvf = not_found hvf = not_found
midl = not_found
widl = not_found
host_dsosuf = '.so' host_dsosuf = '.so'
if targetos == 'windows' if targetos == 'windows'
midl = find_program('midl', required: false)
widl = find_program('widl', required: false)
socket = cc.find_library('ws2_32') socket = cc.find_library('ws2_32')
winmm = cc.find_library('winmm') winmm = cc.find_library('winmm')

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@ -20,6 +20,8 @@ have_qga_vss = get_option('qga_vss') \
$ scripts/extract-vsssdk-headers setup.exe $ scripts/extract-vsssdk-headers setup.exe
The headers are extracted in the directory 'inc/win2003'. The headers are extracted in the directory 'inc/win2003'.
Then run configure with: --extra-cxxflags="-isystem /path/to/vss/inc/win2003"''') \ Then run configure with: --extra-cxxflags="-isystem /path/to/vss/inc/win2003"''') \
.require(midl.found() or widl.found(),
error_message: 'VSS support requires midl or widl') \
.allowed() .allowed()
all_qga = [] all_qga = []

View File

@ -25,21 +25,14 @@ qga_vss = shared_module(
all_qga += qga_vss all_qga += qga_vss
midl = find_program('midl', required: false)
widl = find_program('widl', required: false)
if midl.found() if midl.found()
gen_tlb = custom_target('gen-tlb', gen_tlb = custom_target('gen-tlb',
input: 'qga-vss.idl', input: 'qga-vss.idl',
output: 'qga-vss.tlb', output: 'qga-vss.tlb',
command: [midl, '@INPUT@', '/tlb', '@OUTPUT@']) command: [midl, '@INPUT@', '/tlb', '@OUTPUT@'])
elif widl.found() else
gen_tlb = custom_target('gen-tlb', gen_tlb = custom_target('gen-tlb',
input: 'qga-vss.idl', input: 'qga-vss.idl',
output: 'qga-vss.tlb', output: 'qga-vss.tlb',
command: [widl, '-t', '@INPUT@', '-o', '@OUTPUT@']) command: [widl, '-t', '@INPUT@', '-o', '@OUTPUT@'])
else
gen_tlb = custom_target('gen-tlb',
input: 'qga-vss.tlb',
output: 'qga-vss.tlb',
command: ['cp', '@INPUT@', '@OUTPUT@'])
endif endif

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