mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

tcg/s390x: Implement vector shift operations

Browse Source 
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2020-09-14 19:00:38 -07:00
parent 479b61cbfa
commit 22cb37b417
3 changed files with 99 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
tcg/s390x/tcg-target-con-set.h
View File

@ -24,6 +24,7 @@ C_O1_I2(r, 0, rI)
C_O1_I2(r, 0, rJ) C_O1_I2(r, 0, rJ)
C_O1_I2(r, r, ri) C_O1_I2(r, r, ri)
C_O1_I2(r, rZ, r) C_O1_I2(r, rZ, r)
C_O1_I2(v, v, r)
C_O1_I2(v, v, v) C_O1_I2(v, v, v)
C_O1_I4(r, r, ri, r, 0) C_O1_I4(r, r, ri, r, 0)
C_O1_I4(r, r, ri, rI, 0) C_O1_I4(r, r, ri, rI, 0)

93
tcg/s390x/tcg-target.c.inc
View File

@ -277,6 +277,10 @@ typedef enum S390Opcode {
VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */ VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */
VRRc_VCH = 0xe7fb, /* " */ VRRc_VCH = 0xe7fb, /* " */
VRRc_VCHL = 0xe7f9, /* " */ VRRc_VCHL = 0xe7f9, /* " */
VRRc_VERLLV = 0xe773,
VRRc_VESLV = 0xe770,
VRRc_VESRAV = 0xe77a,
VRRc_VESRLV = 0xe778,
VRRc_VML = 0xe7a2, VRRc_VML = 0xe7a2,
VRRc_VN = 0xe768, VRRc_VN = 0xe768,
VRRc_VNC = 0xe769, VRRc_VNC = 0xe769,
@ -287,6 +291,10 @@ typedef enum S390Opcode {
VRRc_VX = 0xe76d, VRRc_VX = 0xe76d,
VRRf_VLVGP = 0xe762, VRRf_VLVGP = 0xe762,
VRSa_VERLL = 0xe733,
VRSa_VESL = 0xe730,
VRSa_VESRA = 0xe73a,
VRSa_VESRL = 0xe738,
VRSb_VLVG = 0xe722, VRSb_VLVG = 0xe722,
VRSc_VLGV = 0xe721, VRSc_VLGV = 0xe721,
@ -643,6 +651,18 @@ static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op,
tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0)); tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0));
} }
static void tcg_out_insn_VRSa(TCGContext *s, S390Opcode op, TCGReg v1,
intptr_t d2, TCGReg b2, TCGReg v3, int m4)
{
tcg_debug_assert(is_vector_reg(v1));
tcg_debug_assert(d2 >= 0 && d2 <= 0xfff);
tcg_debug_assert(is_general_reg(b2));
tcg_debug_assert(is_vector_reg(v3));
tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf));
tcg_out16(s, b2 << 12 | d2);
tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, v3, 0) | (m4 << 12));
}
static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1, static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1,
intptr_t d2, TCGReg b2, TCGReg r3, int m4) intptr_t d2, TCGReg b2, TCGReg r3, int m4)
{ {
@ -2710,6 +2730,43 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0); tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0);
break; break;
case INDEX_op_shli_vec:
tcg_out_insn(s, VRSa, VESL, a0, a2, TCG_REG_NONE, a1, vece);
break;
case INDEX_op_shri_vec:
tcg_out_insn(s, VRSa, VESRL, a0, a2, TCG_REG_NONE, a1, vece);
break;
case INDEX_op_sari_vec:
tcg_out_insn(s, VRSa, VESRA, a0, a2, TCG_REG_NONE, a1, vece);
break;
case INDEX_op_rotli_vec:
tcg_out_insn(s, VRSa, VERLL, a0, a2, TCG_REG_NONE, a1, vece);
break;
case INDEX_op_shls_vec:
tcg_out_insn(s, VRSa, VESL, a0, 0, a2, a1, vece);
break;
case INDEX_op_shrs_vec:
tcg_out_insn(s, VRSa, VESRL, a0, 0, a2, a1, vece);
break;
case INDEX_op_sars_vec:
tcg_out_insn(s, VRSa, VESRA, a0, 0, a2, a1, vece);
break;
case INDEX_op_rotls_vec:
tcg_out_insn(s, VRSa, VERLL, a0, 0, a2, a1, vece);
break;
case INDEX_op_shlv_vec:
tcg_out_insn(s, VRRc, VESLV, a0, a1, a2, vece);
break;
case INDEX_op_shrv_vec:
tcg_out_insn(s, VRRc, VESRLV, a0, a1, a2, vece);
break;
case INDEX_op_sarv_vec:
tcg_out_insn(s, VRRc, VESRAV, a0, a1, a2, vece);
break;
case INDEX_op_rotlv_vec:
tcg_out_insn(s, VRRc, VERLLV, a0, a1, a2, vece);
break;
case INDEX_op_cmp_vec: case INDEX_op_cmp_vec:
switch ((TCGCond)args[3]) { switch ((TCGCond)args[3]) {
case TCG_COND_EQ: case TCG_COND_EQ:
@ -2744,10 +2801,23 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_not_vec: case INDEX_op_not_vec:
case INDEX_op_or_vec: case INDEX_op_or_vec:
case INDEX_op_orc_vec: case INDEX_op_orc_vec:
case INDEX_op_rotli_vec:
case INDEX_op_rotls_vec:
case INDEX_op_rotlv_vec:
case INDEX_op_sari_vec:
case INDEX_op_sars_vec:
case INDEX_op_sarv_vec:
case INDEX_op_shli_vec:
case INDEX_op_shls_vec:
case INDEX_op_shlv_vec:
case INDEX_op_shri_vec:
case INDEX_op_shrs_vec:
case INDEX_op_shrv_vec:
case INDEX_op_sub_vec: case INDEX_op_sub_vec:
case INDEX_op_xor_vec: case INDEX_op_xor_vec:
return 1; return 1;
case INDEX_op_cmp_vec: case INDEX_op_cmp_vec:
case INDEX_op_rotrv_vec:
return -1; return -1;
case INDEX_op_mul_vec: case INDEX_op_mul_vec:
return vece < MO_64; return vece < MO_64;
@ -2810,7 +2880,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
TCGArg a0, ...) TCGArg a0, ...)
{ {
va_list va; va_list va;
TCGv_vec v0, v1, v2; TCGv_vec v0, v1, v2, t0;
va_start(va, a0); va_start(va, a0);
v0 = temp_tcgv_vec(arg_temp(a0)); v0 = temp_tcgv_vec(arg_temp(a0));
@ -2822,6 +2892,13 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg));
break; break;
case INDEX_op_rotrv_vec:
t0 = tcg_temp_new_vec(type);
tcg_gen_neg_vec(vece, t0, v2);
tcg_gen_rotlv_vec(vece, v0, v1, t0);
tcg_temp_free_vec(t0);
break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
} }
@ -2978,6 +3055,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_abs_vec: case INDEX_op_abs_vec:
case INDEX_op_neg_vec: case INDEX_op_neg_vec:
case INDEX_op_not_vec: case INDEX_op_not_vec:
case INDEX_op_rotli_vec:
case INDEX_op_sari_vec:
case INDEX_op_shli_vec:
case INDEX_op_shri_vec:
return C_O1_I1(v, v); return C_O1_I1(v, v);
case INDEX_op_add_vec: case INDEX_op_add_vec:
case INDEX_op_sub_vec: case INDEX_op_sub_vec:
@ -2988,7 +3069,17 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_xor_vec: case INDEX_op_xor_vec:
case INDEX_op_cmp_vec: case INDEX_op_cmp_vec:
case INDEX_op_mul_vec: case INDEX_op_mul_vec:
case INDEX_op_rotlv_vec:
case INDEX_op_rotrv_vec:
case INDEX_op_shlv_vec:
case INDEX_op_shrv_vec:
case INDEX_op_sarv_vec:
return C_O1_I2(v, v, v); return C_O1_I2(v, v, v);
case INDEX_op_rotls_vec:
case INDEX_op_shls_vec:
case INDEX_op_shrs_vec:
case INDEX_op_sars_vec:
return C_O1_I2(v, v, r);
default: default:
g_assert_not_reached(); g_assert_not_reached();

12
tcg/s390x/tcg-target.h
View File

@ -148,12 +148,12 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_not_vec 1 #define TCG_TARGET_HAS_not_vec 1
#define TCG_TARGET_HAS_neg_vec 1 #define TCG_TARGET_HAS_neg_vec 1
#define TCG_TARGET_HAS_abs_vec 1 #define TCG_TARGET_HAS_abs_vec 1
#define TCG_TARGET_HAS_roti_vec 0 #define TCG_TARGET_HAS_roti_vec 1
#define TCG_TARGET_HAS_rots_vec 0 #define TCG_TARGET_HAS_rots_vec 1
#define TCG_TARGET_HAS_rotv_vec 0 #define TCG_TARGET_HAS_rotv_vec 1
#define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shi_vec 1
#define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shs_vec 1
#define TCG_TARGET_HAS_shv_vec 0 #define TCG_TARGET_HAS_shv_vec 1
#define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 0 #define TCG_TARGET_HAS_sat_vec 0
#define TCG_TARGET_HAS_minmax_vec 0 #define TCG_TARGET_HAS_minmax_vec 0