mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

target/riscv: Start counters from both mhpmcounter and mcountinhibit

Browse Source 
Currently we start timer counter from write_mhpmcounter path only
without checking for mcountinhibit bit. This changes adds mcountinhibit
check and also programs the counter from write_mcountinhibit as well.

When a counter is stopped using mcountinhibit we simply update
the value of the counter based on current host ticks and save
it for future reads.

We don't need to disable running timer as pmu_timer_trigger_irq
will discard the interrupt if the counter has been inhibited.

Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240711-smcntrpmf_v7-v8-10-b7c38ae7b263@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Rajnesh Kanwal 2024-07-11 15:31:13 -07:00 committed by Alistair Francis
parent 8cff74c26d
commit 22c721c34c
2 changed files with 54 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

75
target/riscv/csr.c
View File

@ -1077,8 +1077,9 @@ static RISCVException write_mhpmcounter(CPURISCVState *env, int csrno,
uint64_t mhpmctr_val = val; uint64_t mhpmctr_val = val;
counter->mhpmcounter_val = val; counter->mhpmcounter_val = val;
if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || if (!get_field(env->mcountinhibit, BIT(ctr_idx)) &&
riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) {
counter->mhpmcounter_prev = riscv_pmu_ctr_get_fixed_counters_val(env, counter->mhpmcounter_prev = riscv_pmu_ctr_get_fixed_counters_val(env,
ctr_idx, false); ctr_idx, false);
if (ctr_idx > 2) { if (ctr_idx > 2) {
@ -1106,8 +1107,9 @@ static RISCVException write_mhpmcounterh(CPURISCVState *env, int csrno,
counter->mhpmcounterh_val = val; counter->mhpmcounterh_val = val;
mhpmctr_val = mhpmctr_val | (mhpmctrh_val << 32); mhpmctr_val = mhpmctr_val | (mhpmctrh_val << 32);
if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || if (!get_field(env->mcountinhibit, BIT(ctr_idx)) &&
riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) {
counter->mhpmcounterh_prev = riscv_pmu_ctr_get_fixed_counters_val(env, counter->mhpmcounterh_prev = riscv_pmu_ctr_get_fixed_counters_val(env,
ctr_idx, true); ctr_idx, true);
if (ctr_idx > 2) { if (ctr_idx > 2) {
@ -2170,31 +2172,60 @@ static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
int cidx; int cidx;
PMUCTRState *counter; PMUCTRState *counter;
RISCVCPU *cpu = env_archcpu(env); RISCVCPU *cpu = env_archcpu(env);
uint32_t present_ctrs = cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_IR;
target_ulong updated_ctrs = (env->mcountinhibit ^ val) & present_ctrs;
uint64_t mhpmctr_val, prev_count, curr_count;
/* WARL register - disable unavailable counters; TM bit is always 0 */ /* WARL register - disable unavailable counters; TM bit is always 0 */
env->mcountinhibit = env->mcountinhibit = val & present_ctrs;
val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_IR);
/* Check if any other counter is also monitoring cycles/instructions */ /* Check if any other counter is also monitoring cycles/instructions */
for (cidx = 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) { for (cidx = 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) {
counter = &env->pmu_ctrs[cidx]; if (!(updated_ctrs & BIT(cidx)) ||
if (get_field(env->mcountinhibit, BIT(cidx)) && (val & BIT(cidx))) { (!riscv_pmu_ctr_monitor_cycles(env, cidx) &&
/* !riscv_pmu_ctr_monitor_instructions(env, cidx))) {
* Update the counter value for cycle/instret as we can't stop the continue;
* host ticks. But we should show the current value at this moment. }
*/
if (riscv_pmu_ctr_monitor_cycles(env, cidx) || counter = &env->pmu_ctrs[cidx];
riscv_pmu_ctr_monitor_instructions(env, cidx)) {
counter->mhpmcounter_val = if (!get_field(env->mcountinhibit, BIT(cidx))) {
riscv_pmu_ctr_get_fixed_counters_val(env, cidx, false) - counter->mhpmcounter_prev =
counter->mhpmcounter_prev + riscv_pmu_ctr_get_fixed_counters_val(env, cidx, false);
counter->mhpmcounter_val; if (riscv_cpu_mxl(env) == MXL_RV32) {
counter->mhpmcounterh_prev =
riscv_pmu_ctr_get_fixed_counters_val(env, cidx, true);
}
if (cidx > 2) {
mhpmctr_val = counter->mhpmcounter_val;
if (riscv_cpu_mxl(env) == MXL_RV32) { if (riscv_cpu_mxl(env) == MXL_RV32) {
counter->mhpmcounterh_val = mhpmctr_val = mhpmctr_val |
riscv_pmu_ctr_get_fixed_counters_val(env, cidx, true) - ((uint64_t)counter->mhpmcounterh_val << 32);
counter->mhpmcounterh_prev +
counter->mhpmcounterh_val;
} }
riscv_pmu_setup_timer(env, mhpmctr_val, cidx);
}
} else {
curr_count = riscv_pmu_ctr_get_fixed_counters_val(env, cidx, false);
mhpmctr_val = counter->mhpmcounter_val;
prev_count = counter->mhpmcounter_prev;
if (riscv_cpu_mxl(env) == MXL_RV32) {
uint64_t tmp =
riscv_pmu_ctr_get_fixed_counters_val(env, cidx, true);
curr_count = curr_count | (tmp << 32);
mhpmctr_val = mhpmctr_val |
((uint64_t)counter->mhpmcounterh_val << 32);
prev_count = prev_count |
((uint64_t)counter->mhpmcounterh_prev << 32);
}
/* Adjust the counter for later reads. */
mhpmctr_val = curr_count - prev_count + mhpmctr_val;
counter->mhpmcounter_val = mhpmctr_val;
if (riscv_cpu_mxl(env) == MXL_RV32) {
counter->mhpmcounterh_val = mhpmctr_val >> 32;
} }
} }
} }

3
target/riscv/pmu.c
View File

@ -285,8 +285,7 @@ int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx)
} }
ctr_idx = GPOINTER_TO_UINT(value); ctr_idx = GPOINTER_TO_UINT(value);
if (!riscv_pmu_counter_enabled(cpu, ctr_idx) || if (!riscv_pmu_counter_enabled(cpu, ctr_idx)) {
get_field(env->mcountinhibit, BIT(ctr_idx))) {
return -1; return -1;
} }