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target-sh4: implement addc and subc using TCG

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Now that setcond is available, the addc and subc can easily be
implemented using TCG.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno 2012-09-16 13:12:20 +02:00
parent ff2086fed2
commit 22b88fd77e
3 changed files with 36 additions and 36 deletions
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2
target-sh4/helper.h
View File

@ -14,9 +14,7 @@ DEF_HELPER_1(discard_movcal_backup, void, env)
DEF_HELPER_2(ocbi, void, env, i32)
DEF_HELPER_3(addv, i32, env, i32, i32)
DEF_HELPER_3(addc, i32, env, i32, i32)
DEF_HELPER_3(subv, i32, env, i32, i32)
DEF_HELPER_3(subc, i32, env, i32, i32)
DEF_HELPER_3(div1, i32, env, i32, i32)
DEF_HELPER_3(macl, void, env, i32, i32)
DEF_HELPER_3(macw, void, env, i32, i32)

32
target-sh4/op_helper.c
View File

@ -177,22 +177,6 @@ void helper_ocbi(CPUSH4State *env, uint32_t address)
}
}
uint32_t helper_addc(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
{
uint32_t tmp0, tmp1;
tmp1 = arg0 + arg1;
tmp0 = arg1;
arg1 = tmp1 + (env->sr & 1);
if (tmp0 > tmp1)
env->sr |= SR_T;
else
env->sr &= ~SR_T;
if (tmp1 > arg1)
env->sr |= SR_T;
return arg1;
}
uint32_t helper_addv(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
{
uint32_t dest, src, ans;
@ -375,22 +359,6 @@ void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
}
}
uint32_t helper_subc(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
{
uint32_t tmp0, tmp1;
tmp1 = arg1 - arg0;
tmp0 = arg1;
arg1 = tmp1 - (env->sr & SR_T);
if (tmp0 < tmp1)
env->sr |= SR_T;
else
env->sr &= ~SR_T;
if (tmp1 < arg1)
env->sr |= SR_T;
return arg1;
}
uint32_t helper_subv(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
{
int32_t dest, src, ans;

38
target-sh4/translate.c
View File

@ -761,7 +761,24 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4));
return;
case 0x300e: /* addc Rm,Rn */
gen_helper_addc(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8));
{
TCGv t0, t1, t2;
t0 = tcg_temp_new();
tcg_gen_andi_i32(t0, cpu_sr, SR_T);
t1 = tcg_temp_new();
tcg_gen_add_i32(t1, REG(B7_4), REG(B11_8));
tcg_gen_add_i32(t0, t0, t1);
t2 = tcg_temp_new();
tcg_gen_setcond_i32(TCG_COND_GTU, t2, REG(B11_8), t1);
tcg_gen_setcond_i32(TCG_COND_GTU, t1, t1, t0);
tcg_gen_or_i32(t1, t1, t2);
tcg_temp_free(t2);
tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
tcg_gen_or_i32(cpu_sr, cpu_sr, t1);
tcg_temp_free(t1);
tcg_gen_mov_i32(REG(B11_8), t0);
tcg_temp_free(t0);
}
return;
case 0x300f: /* addv Rm,Rn */
gen_helper_addv(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8));
@ -1013,7 +1030,24 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_sub_i32(REG(B11_8), REG(B11_8), REG(B7_4));
return;
case 0x300a: /* subc Rm,Rn */
gen_helper_subc(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8));
{
TCGv t0, t1, t2;
t0 = tcg_temp_new();
tcg_gen_andi_i32(t0, cpu_sr, SR_T);
t1 = tcg_temp_new();
tcg_gen_sub_i32(t1, REG(B11_8), REG(B7_4));
tcg_gen_sub_i32(t0, t1, t0);
t2 = tcg_temp_new();
tcg_gen_setcond_i32(TCG_COND_LTU, t2, REG(B11_8), t1);
tcg_gen_setcond_i32(TCG_COND_LTU, t1, t1, t0);
tcg_gen_or_i32(t1, t1, t2);
tcg_temp_free(t2);
tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
tcg_gen_or_i32(cpu_sr, cpu_sr, t1);
tcg_temp_free(t1);
tcg_gen_mov_i32(REG(B11_8), t0);
tcg_temp_free(t0);
}
return;
case 0x300b: /* subv Rm,Rn */
gen_helper_subv(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8));