PPC: Add MPC8XXX gpio controller
On e500 systems most SoCs implement a common GPIO controller that Linux calls the "mpc8xxx" gpio controller. This patch adds an emulation model for this device. Signed-off-by: Alexander Graf <agraf@suse.de>
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Alexander Graf
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81f194dd69
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228aa992fc
@ -2,5 +2,6 @@ common-obj-$(CONFIG_MAX7310) += max7310.o
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common-obj-$(CONFIG_PL061) += pl061.o
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common-obj-$(CONFIG_PUV3) += puv3_gpio.o
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common-obj-$(CONFIG_ZAURUS) += zaurus.o
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common-obj-$(CONFIG_E500) += mpc8xxx.o
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obj-$(CONFIG_OMAP) += omap_gpio.o
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217
hw/gpio/mpc8xxx.c
Normal file
217
hw/gpio/mpc8xxx.c
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@ -0,0 +1,217 @@
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/*
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* GPIO Controller for a lot of Freescale SoCs
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*
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* Copyright (C) 2014 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Author: Alexander Graf, <agraf@suse.de>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw/sysbus.h"
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#define TYPE_MPC8XXX_GPIO "mpc8xxx_gpio"
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#define MPC8XXX_GPIO(obj) OBJECT_CHECK(MPC8XXXGPIOState, (obj), TYPE_MPC8XXX_GPIO)
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typedef struct MPC8XXXGPIOState {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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qemu_irq irq;
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qemu_irq out[32];
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uint32_t dir;
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uint32_t odr;
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uint32_t dat;
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uint32_t ier;
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uint32_t imr;
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uint32_t icr;
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} MPC8XXXGPIOState;
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static const VMStateDescription vmstate_mpc8xxx_gpio = {
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.name = "mpc8xxx_gpio",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(dir, MPC8XXXGPIOState),
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VMSTATE_UINT32(odr, MPC8XXXGPIOState),
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VMSTATE_UINT32(dat, MPC8XXXGPIOState),
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VMSTATE_UINT32(ier, MPC8XXXGPIOState),
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VMSTATE_UINT32(imr, MPC8XXXGPIOState),
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VMSTATE_UINT32(icr, MPC8XXXGPIOState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void mpc8xxx_gpio_update(MPC8XXXGPIOState *s)
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{
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qemu_set_irq(s->irq, !!(s->ier & s->imr));
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}
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static uint64_t mpc8xxx_gpio_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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MPC8XXXGPIOState *s = (MPC8XXXGPIOState *)opaque;
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if (size != 4) {
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/* All registers are 32bit */
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return 0;
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}
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switch (offset) {
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case 0x0: /* Direction */
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return s->dir;
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case 0x4: /* Open Drain */
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return s->odr;
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case 0x8: /* Data */
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return s->dat;
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case 0xC: /* Interrupt Event */
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return s->ier;
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case 0x10: /* Interrupt Mask */
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return s->imr;
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case 0x14: /* Interrupt Control */
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return s->icr;
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default:
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return 0;
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}
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}
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static void mpc8xxx_write_data(MPC8XXXGPIOState *s, uint32_t new_data)
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{
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uint32_t old_data = s->dat;
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uint32_t diff = old_data ^ new_data;
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int i;
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for (i = 0; i < 32; i++) {
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uint32_t mask = 0x80000000 >> i;
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if (!(diff & mask)) {
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continue;
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}
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if (s->dir & mask) {
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/* Output */
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qemu_set_irq(s->out[i], (new_data & mask) != 0);
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}
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}
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s->dat = new_data;
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}
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static void mpc8xxx_gpio_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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MPC8XXXGPIOState *s = (MPC8XXXGPIOState *)opaque;
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if (size != 4) {
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/* All registers are 32bit */
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return;
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}
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switch (offset) {
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case 0x0: /* Direction */
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s->dir = value;
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break;
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case 0x4: /* Open Drain */
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s->odr = value;
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break;
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case 0x8: /* Data */
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mpc8xxx_write_data(s, value);
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break;
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case 0xC: /* Interrupt Event */
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s->ier &= ~value;
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break;
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case 0x10: /* Interrupt Mask */
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s->imr = value;
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break;
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case 0x14: /* Interrupt Control */
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s->icr = value;
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break;
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}
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mpc8xxx_gpio_update(s);
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}
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static void mpc8xxx_gpio_reset(MPC8XXXGPIOState *s)
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{
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s->dir = 0;
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s->odr = 0;
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s->dat = 0;
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s->ier = 0;
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s->imr = 0;
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s->icr = 0;
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}
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static void mpc8xxx_gpio_set_irq(void * opaque, int irq, int level)
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{
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MPC8XXXGPIOState *s = (MPC8XXXGPIOState *)opaque;
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uint32_t mask;
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mask = 0x80000000 >> irq;
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if ((s->dir & mask) == 0) {
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uint32_t old_value = s->dat & mask;
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s->dat &= ~mask;
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if (level)
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s->dat |= mask;
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if (!(s->icr & irq) || (old_value && !level)) {
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s->ier |= mask;
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}
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mpc8xxx_gpio_update(s);
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}
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}
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static const MemoryRegionOps mpc8xxx_gpio_ops = {
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.read = mpc8xxx_gpio_read,
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.write = mpc8xxx_gpio_write,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static int mpc8xxx_gpio_initfn(SysBusDevice *sbd)
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{
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DeviceState *dev = DEVICE(sbd);
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MPC8XXXGPIOState *s = MPC8XXX_GPIO(dev);
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memory_region_init_io(&s->iomem, OBJECT(s), &mpc8xxx_gpio_ops, s, "mpc8xxx_gpio", 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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sysbus_init_irq(sbd, &s->irq);
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qdev_init_gpio_in(dev, mpc8xxx_gpio_set_irq, 32);
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qdev_init_gpio_out(dev, s->out, 32);
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mpc8xxx_gpio_reset(s);
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return 0;
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}
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static void mpc8xxx_gpio_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = mpc8xxx_gpio_initfn;
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dc->vmsd = &vmstate_mpc8xxx_gpio;
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}
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static const TypeInfo mpc8xxx_gpio_info = {
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.name = TYPE_MPC8XXX_GPIO,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(MPC8XXXGPIOState),
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.class_init = mpc8xxx_gpio_class_init,
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};
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static void mpc8xxx_gpio_register_types(void)
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{
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type_register_static(&mpc8xxx_gpio_info);
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}
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type_init(mpc8xxx_gpio_register_types)
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