pci, virtio bugfixes for 2.3
Just a bunch of bugfixes. Should be nothing remarkable here. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJVCXAHAAoJECgfDbjSjVRp6zcH/A1NwWCefPfGj2wLc/GdhKJ4 NcxNYQwNh/C687BKV+iBFvUqh+G1lkuoz7OYX+EGvzadqeWmDX7uIhCm8z01aqb0 La/afm/JyB22Vz7Za1od+JUyjwSJoyBiD/1OI/lS6/6fPLtj1vwnyC4V6zmJgXDt OvWKYk/xexMSnQH8Gutw74Kasdvh+ui1l2T1Ti5VlYY5Ea6a36dDxqKhdMOdMOpE 5zAQHNGYihtQhxjJPUdvoCR0zNknNGd62XpMBk7mEvB98yCZnLLZ/HnbeDjUV9gN Lj8yG1nbsiGA2uu4XHD+PTHW3wN0K/DDM9XDDGOHuh7jsBB7XSrVBD/TnQuUmUg= =sL0e -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging pci, virtio bugfixes for 2.3 Just a bunch of bugfixes. Should be nothing remarkable here. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Wed Mar 18 12:31:03 2015 GMT using RSA key ID D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: pcie_aer: fix comment to match pcie spec pci: fix several trivial typos in comment aer: fix a wrong init PCI_ERR_COR_STATUS w1cmask type register pcie_aer: fix typos in pcie_aer_inject_error comment aer: fix wrong check on expose aer tlp prefix log pcie: correct mistaken register bit for End-End TLP Prefix Blocking virtio: Fix memory leaks reported by Coverity virtio: validate the existence of handle_output before calling it Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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commit
2259c16dc2
@ -84,7 +84,7 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port)
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pci_set_long(exp_cap + PCI_EXP_DEVCAP2,
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PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP);
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pci_set_word(dev->wmask + pos, PCI_EXP_DEVCTL2_EETLPPB);
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pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB);
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return pos;
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}
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@ -123,7 +123,7 @@ int pcie_aer_init(PCIDevice *dev, uint16_t offset)
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PCI_ERR_UNC_SUPPORTED);
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pci_long_test_and_set_mask(dev->w1cmask + offset + PCI_ERR_COR_STATUS,
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PCI_ERR_COR_STATUS);
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PCI_ERR_COR_SUPPORTED);
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pci_set_long(dev->config + offset + PCI_ERR_COR_MASK,
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PCI_ERR_COR_MASK_DEFAULT);
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@ -433,7 +433,7 @@ static void pcie_aer_update_log(PCIDevice *dev, const PCIEAERErr *err)
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}
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if ((err->flags & PCIE_AER_ERR_TLP_PREFIX_PRESENT) &&
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(pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) &
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(pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP2) &
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PCI_EXP_DEVCAP2_EETLPP)) {
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for (i = 0; i < ARRAY_SIZE(err->prefix); ++i) {
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/* 7.10.12 tlp prefix log register */
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@ -618,12 +618,12 @@ static bool pcie_aer_inject_uncor_error(PCIEAERInject *inj, bool is_fatal)
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* non-Function specific error must be recorded in all functions.
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* It is the responsibility of the caller of this function.
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* It is also caller's responsibility to determine which function should
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* report the rerror.
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* report the error.
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*
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* 6.2.4 Error Logging
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* 6.2.5 Sqeunce of Device Error Signaling and Logging Operations
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* table 6-2: Flowchard Showing Sequence of Device Error Signaling and Logging
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* Operations
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* 6.2.5 Sequence of Device Error Signaling and Logging Operations
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* Figure 6-2: Flowchart Showing Sequence of Device Error Signaling and Logging
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* Operations
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*/
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int pcie_aer_inject_error(PCIDevice *dev, const PCIEAERErr *err)
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{
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@ -759,8 +759,9 @@ void virtio_queue_set_align(VirtIODevice *vdev, int n, int align)
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void virtio_queue_notify_vq(VirtQueue *vq)
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{
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if (vq->vring.desc) {
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if (vq->vring.desc && vq->handle_output) {
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VirtIODevice *vdev = vq->vdev;
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trace_virtio_queue_notify(vdev, vq - vdev->vq, vq);
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vq->handle_output(vdev, vq);
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}
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@ -137,7 +137,7 @@ enum {
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#define PCI_CONFIG_HEADER_SIZE 0x40
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/* Size of the standard PCI config space */
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#define PCI_CONFIG_SPACE_SIZE 0x100
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/* Size of the standart PCIe config space: 4KB */
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/* Size of the standard PCIe config space: 4KB */
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#define PCIE_CONFIG_SPACE_SIZE 0x1000
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#define PCI_NUM_PINS 4 /* A-D */
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@ -51,7 +51,7 @@ struct PCIEAERLog {
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PCIEAERErr *log;
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};
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/* aer error message: error signaling message has only error sevirity and
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/* aer error message: error signaling message has only error severity and
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source id. See 2.2.8.3 error signaling messages */
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struct PCIEAERMsg {
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/*
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@ -72,7 +72,7 @@
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#define PCI_EXP_DEVCAP2_EFF 0x100000
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#define PCI_EXP_DEVCAP2_EETLPP 0x200000
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#define PCI_EXP_DEVCTL2_EETLPPB 0x80
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#define PCI_EXP_DEVCTL2_EETLPPB 0x8000
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/* ARI */
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#define PCI_ARI_VER 1
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