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target/arm: Convert SRSHL, URSHL to decodetree 

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240528203044.612851-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-05-28 13:30:22 -07:00 committed by Peter Maydell
parent 940392c834
commit 2214c9d721
2 changed files with 11 additions and 15 deletions
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4
target/arm/tcg/a64.decode
View File

@ -758,6 +758,8 @@ USQADD_s 0111 1110 ..1 00000 00111 0 ..... ..... @r2r_e
SSHL_s 0101 1110 111 ..... 01000 1 ..... ..... @rrr_d
USHL_s 0111 1110 111 ..... 01000 1 ..... ..... @rrr_d
SRSHL_s 0101 1110 111 ..... 01010 1 ..... ..... @rrr_d
URSHL_s 0111 1110 111 ..... 01010 1 ..... ..... @rrr_d
### Advanced SIMD scalar pairwise
@ -882,6 +884,8 @@ USQADD_v 0.10 1110 ..1 00000 00111 0 ..... ..... @qr2r_e
SSHL_v 0.00 1110 ..1 ..... 01000 1 ..... ..... @qrrr_e
USHL_v 0.10 1110 ..1 ..... 01000 1 ..... ..... @qrrr_e
SRSHL_v 0.00 1110 ..1 ..... 01010 1 ..... ..... @qrrr_e
URSHL_v 0.10 1110 ..1 ..... 01010 1 ..... ..... @qrrr_e
### Advanced SIMD scalar x indexed element

22
target/arm/tcg/translate-a64.c
View File

@ -5116,6 +5116,8 @@ static bool do_int3_scalar_d(DisasContext *s, arg_rrr_e *a,
TRANS(SSHL_s, do_int3_scalar_d, a, gen_sshl_i64)
TRANS(USHL_s, do_int3_scalar_d, a, gen_ushl_i64)
TRANS(SRSHL_s, do_int3_scalar_d, a, gen_helper_neon_rshl_s64)
TRANS(URSHL_s, do_int3_scalar_d, a, gen_helper_neon_rshl_u64)
static bool do_fp3_vector(DisasContext *s, arg_qrrr_e *a,
gen_helper_gvec_3_ptr * const fns[3])
@ -5364,6 +5366,8 @@ TRANS(USQADD_v, do_gvec_fn3, a, gen_gvec_usqadd_qc)
TRANS(SSHL_v, do_gvec_fn3, a, gen_gvec_sshl)
TRANS(USHL_v, do_gvec_fn3, a, gen_gvec_ushl)
TRANS(SRSHL_v, do_gvec_fn3, a, gen_gvec_srshl)
TRANS(URSHL_v, do_gvec_fn3, a, gen_gvec_urshl)
/*
@ -9384,13 +9388,6 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u,
gen_helper_neon_qshl_s64(tcg_rd, tcg_env, tcg_rn, tcg_rm);
}
break;
case 0xa: /* SRSHL, URSHL */
if (u) {
gen_helper_neon_rshl_u64(tcg_rd, tcg_rn, tcg_rm);
} else {
gen_helper_neon_rshl_s64(tcg_rd, tcg_rn, tcg_rm);
}
break;
case 0xb: /* SQRSHL, UQRSHL */
if (u) {
gen_helper_neon_qrshl_u64(tcg_rd, tcg_env, tcg_rn, tcg_rm);
@ -9409,6 +9406,7 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u,
case 0x1: /* SQADD / UQADD */
case 0x5: /* SQSUB / UQSUB */
case 0x8: /* SSHL, USHL */
case 0xa: /* SRSHL, URSHL */
g_assert_not_reached();
}
}
@ -9433,7 +9431,6 @@ static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn)
case 0x9: /* SQSHL, UQSHL */
case 0xb: /* SQRSHL, UQRSHL */
break;
case 0xa: /* SRSHL, URSHL */
case 0x6: /* CMGT, CMHI */
case 0x7: /* CMGE, CMHS */
case 0x11: /* CMTST, CMEQ */
@ -9453,6 +9450,7 @@ static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn)
case 0x1: /* SQADD, UQADD */
case 0x5: /* SQSUB, UQSUB */
case 0x8: /* SSHL, USHL */
case 0xa: /* SRSHL, URSHL */
unallocated_encoding(s);
return;
}
@ -10929,6 +10927,7 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
case 0x01: /* SQADD, UQADD */
case 0x05: /* SQSUB, UQSUB */
case 0x08: /* SSHL, USHL */
case 0x0a: /* SRSHL, URSHL */
unallocated_encoding(s);
return;
}
@ -10938,13 +10937,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
}
switch (opcode) {
case 0x0a: /* SRSHL, URSHL */
if (u) {
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_urshl, size);
} else {
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_srshl, size);
}
return;
case 0x0c: /* SMAX, UMAX */
if (u) {
gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umax, size);