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hw/riscv: sifive_u: Remove compile time XLEN checks

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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: 40d6df4dd05302c566e419be3a1fef7799e57c2e.1608142916.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis 2020-12-16 10:22:45 -08:00
parent bd62c13ea8
commit 2206ffa68f
1 changed files with 30 additions and 25 deletions
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49
hw/riscv/sifive_u.c
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@ -60,12 +60,6 @@
#include <libfdt.h> #include <libfdt.h>
#if defined(TARGET_RISCV32)
# define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.bin"
#else
# define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.bin"
#endif
static const struct MemmapEntry { static const struct MemmapEntry {
hwaddr base; hwaddr base;
hwaddr size; hwaddr size;
@ -93,7 +87,7 @@ static const struct MemmapEntry {
#define GEM_REVISION 0x10070109 #define GEM_REVISION 0x10070109
static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
uint64_t mem_size, const char *cmdline) uint64_t mem_size, const char *cmdline, bool is_32_bit)
{ {
MachineState *ms = MACHINE(qdev_get_machine()); MachineState *ms = MACHINE(qdev_get_machine());
void *fdt; void *fdt;
@ -176,11 +170,11 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_add_subnode(fdt, nodename);
/* cpu 0 is the management hart that does not have mmu */ /* cpu 0 is the management hart that does not have mmu */
if (cpu != 0) { if (cpu != 0) {
#if defined(TARGET_RISCV32) if (is_32_bit) {
qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
#else } else {
qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
#endif }
isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
} else { } else {
isa = riscv_isa_string(&s->soc.e_cpus.harts[0]); isa = riscv_isa_string(&s->soc.e_cpus.harts[0]);
@ -471,7 +465,8 @@ static void sifive_u_machine_init(MachineState *machine)
qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); qemu_allocate_irq(sifive_u_machine_reset, NULL, 0));
/* create device tree */ /* create device tree */
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
riscv_is_32_bit(machine));
if (s->start_in_flash) { if (s->start_in_flash) {
/* /*
@ -500,8 +495,15 @@ static void sifive_u_machine_init(MachineState *machine)
break; break;
} }
firmware_end_addr = riscv_find_and_load_firmware(machine, BIOS_FILENAME, if (riscv_is_32_bit(machine)) {
firmware_end_addr = riscv_find_and_load_firmware(machine,
"opensbi-riscv32-generic-fw_dynamic.bin",
start_addr, NULL); start_addr, NULL);
} else {
firmware_end_addr = riscv_find_and_load_firmware(machine,
"opensbi-riscv64-generic-fw_dynamic.bin",
start_addr, NULL);
}
if (machine->kernel_filename) { if (machine->kernel_filename) {
kernel_start_addr = riscv_calc_kernel_start_addr(machine, kernel_start_addr = riscv_calc_kernel_start_addr(machine,
@ -531,9 +533,9 @@ static void sifive_u_machine_init(MachineState *machine)
/* Compute the fdt load address in dram */ /* Compute the fdt load address in dram */
fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
machine->ram_size, s->fdt); machine->ram_size, s->fdt);
#if defined(TARGET_RISCV64) if (!riscv_is_32_bit(machine)) {
start_addr_hi32 = start_addr >> 32; start_addr_hi32 = (uint64_t)start_addr >> 32;
#endif }
/* reset vector */ /* reset vector */
uint32_t reset_vec[11] = { uint32_t reset_vec[11] = {
@ -541,13 +543,8 @@ static void sifive_u_machine_init(MachineState *machine)
0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
0xf1402573, /* csrr a0, mhartid */ 0xf1402573, /* csrr a0, mhartid */
#if defined(TARGET_RISCV32) 0,
0x0202a583, /* lw a1, 32(t0) */ 0,
0x0182a283, /* lw t0, 24(t0) */
#elif defined(TARGET_RISCV64)
0x0202b583, /* ld a1, 32(t0) */
0x0182b283, /* ld t0, 24(t0) */
#endif
0x00028067, /* jr t0 */ 0x00028067, /* jr t0 */
start_addr, /* start: .dword */ start_addr, /* start: .dword */
start_addr_hi32, start_addr_hi32,
@ -555,6 +552,14 @@ static void sifive_u_machine_init(MachineState *machine)
0x00000000, 0x00000000,
/* fw_dyn: */ /* fw_dyn: */
}; };
if (riscv_is_32_bit(machine)) {
reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */
reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */
} else {
reset_vec[4] = 0x0202b583; /* ld a1, 32(t0) */
reset_vec[5] = 0x0182b283; /* ld t0, 24(t0) */
}
/* copy in the reset vector in little_endian byte order */ /* copy in the reset vector in little_endian byte order */
for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {