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xilinx_spips: Fix CTRL register RW bits 

The CTRL register was RAZ/WI on some of the RW bits. Even though the
function behind these bits is invalid in QEMU, they should still be
guest accessible. Fix.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Message-id: b7aaad93163ce4af0c428635804ac7b77a567b25.1369117359.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Crosthwaite 2013-06-03 17:17:43 +01:00 committed by Peter Maydell
parent 15408b428f
commit 2133a5f6b8
1 changed files with 3 additions and 2 deletions
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5
hw/ssi/xilinx_spips.c
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@ -56,6 +56,7 @@
#define CLK_PH (1 << 2)
#define CLK_POL (1 << 1)
#define MODE_SEL (1 << 0)
#define R_CONFIG_RSVD (0x7bf40000)
/* interrupt mechanism */
#define R_INTR_STATUS (0x04 / 4)
@ -355,7 +356,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
addr >>= 2;
switch (addr) {
case R_CONFIG:
mask = 0x0002FFFF;
mask = ~(R_CONFIG_RSVD | MAN_START_COM);
break;
case R_INTR_STATUS:
ret = s->regs[addr] & IXR_ALL;
@ -415,7 +416,7 @@ static void xilinx_spips_write(void *opaque, hwaddr addr,
addr >>= 2;
switch (addr) {
case R_CONFIG:
mask = 0x0002FFFF;
mask = ~(R_CONFIG_RSVD | MAN_START_COM);
if (value & MAN_START_COM) {
man_start_com = 1;
}