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hw/isa/lpc_ich9: Connect PM stuff to LPC internally

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Make TYPE_ICH9_LPC_DEVICE more self-contained by moving the call to
ich9_lpc_pm_init() from board code to its realize function. In order
to propagate x86_machine_is_smm_enabled(), introduce an "smm-enabled"
property like we have in piix4.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230213173033.98762-8-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Bernhard Beschow 2023-02-13 18:30:28 +01:00 committed by Philippe Mathieu-Daudé
parent ecf403cbb8
commit 20fe3af24f
5 changed files with 11 additions and 18 deletions
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8
hw/acpi/ich9.c
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@ -291,9 +291,7 @@ static void pm_powerdown_req(Notifier *n, void *opaque)
acpi_pm1_evt_power_down(&pm->acpi_regs);
}
void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
bool smm_enabled,
qemu_irq sci_irq)
void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, qemu_irq sci_irq)
{
memory_region_init(&pm->io, OBJECT(lpc_pci), "ich9-pm", ICH9_PMIO_SIZE);
memory_region_set_enabled(&pm->io, false);
@ -303,7 +301,7 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io, pm->disable_s3, pm->disable_s4,
pm->s4_val, !pm->smm_compat && !smm_enabled);
pm->s4_val, !pm->smm_compat && !pm->smm_enabled);
acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
memory_region_init_io(&pm->io_gpe, OBJECT(lpc_pci), &ich9_gpe_ops, pm,
@ -314,8 +312,6 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
"acpi-smi", 8);
memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi);
pm->smm_enabled = smm_enabled;
if (pm->enable_tco) {
acpi_pm_tco_init(&pm->tco_regs, &pm->io);
}

5
hw/i386/pc_q35.c
View File

@ -237,6 +237,8 @@ static void pc_q35_init(MachineState *machine)
/* create ISA bus */
lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), true,
TYPE_ICH9_LPC_DEVICE);
qdev_prop_set_bit(DEVICE(lpc), "smm-enabled",
x86_machine_is_smm_enabled(x86ms));
pci_realize_and_unref(lpc, host_bus, &error_fatal);
object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
@ -291,9 +293,6 @@ static void pc_q35_init(MachineState *machine)
pc_basic_device_init(pcms, isa_bus, x86ms->gsi, &rtc_state, !mc->no_floppy,
0xff0104);
/* connect pm stuff to lpc */
ich9_lpc_pm_init(lpc, x86_machine_is_smm_enabled(x86ms));
if (pcms->sata_enabled) {
/* ahci and SATA device, for q35 1 ahci controller is built-in */
ahci = pci_create_simple_multifunction(host_bus,

8
hw/isa/lpc_ich9.c
View File

@ -407,14 +407,13 @@ static void smi_features_ok_callback(void *opaque)
lpc->smi_features_ok = 1;
}
void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled)
static void ich9_lpc_pm_init(ICH9LPCState *lpc)
{
ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci);
qemu_irq sci_irq;
FWCfgState *fw_cfg = fw_cfg_find();
sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0);
ich9_pm_init(lpc_pci, &lpc->pm, smm_enabled, sci_irq);
ich9_pm_init(PCI_DEVICE(lpc), &lpc->pm, sci_irq);
if (lpc->smi_host_features && fw_cfg) {
uint64_t host_features_le;
@ -731,6 +730,8 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp)
pci_bus_irqs(pci_bus, ich9_lpc_set_irq, d, ICH9_LPC_NB_PIRQS);
pci_bus_map_irqs(pci_bus, ich9_lpc_map_irq);
pci_bus_set_route_irq_fn(pci_bus, ich9_route_intx_pin_to_irq);
ich9_lpc_pm_init(lpc);
}
static bool ich9_rst_cnt_needed(void *opaque)
@ -797,6 +798,7 @@ static const VMStateDescription vmstate_ich9_lpc = {
static Property ich9_lpc_properties[] = {
DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, false),
DEFINE_PROP_BOOL("smm-compat", ICH9LPCState, pm.smm_compat, false),
DEFINE_PROP_BOOL("smm-enabled", ICH9LPCState, pm.smm_enabled, false),
DEFINE_PROP_BIT64("x-smi-broadcast", ICH9LPCState, smi_host_features,
ICH9_LPC_SMI_F_BROADCAST_BIT, true),
DEFINE_PROP_BIT64("x-smi-cpu-hotplug", ICH9LPCState, smi_host_features,

6
include/hw/acpi/ich9.h
View File

@ -64,7 +64,7 @@ typedef struct ICH9LPCPMRegs {
uint8_t disable_s3;
uint8_t disable_s4;
uint8_t s4_val;
uint8_t smm_enabled;
bool smm_enabled;
bool smm_compat;
bool enable_tco;
TCOIORegs tco_regs;
@ -72,9 +72,7 @@ typedef struct ICH9LPCPMRegs {
#define ACPI_PM_PROP_TCO_ENABLED "enable_tco"
void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
bool smm_enabled,
qemu_irq sci_irq);
void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, qemu_irq sci_irq);
void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base);
extern const VMStateDescription vmstate_ich9_pm;

2
include/hw/i386/ich9.h
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@ -8,8 +8,6 @@
#include "hw/acpi/ich9.h"
#include "qom/object.h"
void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled);
void ich9_generate_smi(void);
#define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */