mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

tcg/mips: Support bswap flags in tcg_out_bswap32

Browse Source 
Merge tcg_out_bswap32 and tcg_out_bswap32s.
Use the flags in the internal uses for loads and stores.

For mips32r2 bswap32 with zero-extension, standardize on
WSBH+ROTR+DEXT.  This is the same number of insns as the
previous DSBH+DSHD+DSRL but fits in better with the flags check.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-06-13 12:21:20 -07:00
parent 27362b7b2c
commit 1fce653440
1 changed files with 16 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

39
tcg/mips/tcg-target.c.inc
View File

@ -579,27 +579,20 @@ static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub)
tcg_debug_assert(ok);
}
static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg)
static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags)
{
if (use_mips32r2_instructions) {
tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16);
if (flags & TCG_BSWAP_OZ) {
tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0);
}
} else {
tcg_out_bswap_subr(s, bswap32_addr);
/* delay slot -- never omit the insn, like tcg_out_mov might. */
tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
}
}
static void tcg_out_bswap32u(TCGContext *s, TCGReg ret, TCGReg arg)
{
if (use_mips32r2_instructions) {
tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
tcg_out_dsrl(s, ret, ret, 32);
} else {
tcg_out_bswap_subr(s, bswap32u_addr);
if (flags & TCG_BSWAP_OZ) {
tcg_out_bswap_subr(s, bswap32u_addr);
} else {
tcg_out_bswap_subr(s, bswap32_addr);
}
/* delay slot -- never omit the insn, like tcg_out_mov might. */
tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
@ -1381,7 +1374,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
if (TCG_TARGET_REG_BITS == 64 && is_64) {
if (use_mips32r2_instructions) {
tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
tcg_out_bswap32u(s, lo, lo);
tcg_out_bswap32(s, lo, lo, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
} else {
tcg_out_bswap_subr(s, bswap32u_addr);
/* delay slot */
@ -1394,7 +1387,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
case MO_SL | MO_BSWAP:
if (use_mips32r2_instructions) {
tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
tcg_out_bswap32(s, lo, lo);
tcg_out_bswap32(s, lo, lo, 0);
} else {
tcg_out_bswap_subr(s, bswap32_addr);
/* delay slot */
@ -1520,7 +1513,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
break;
case MO_32 | MO_BSWAP:
tcg_out_bswap32(s, TCG_TMP3, lo);
tcg_out_bswap32(s, TCG_TMP3, lo, 0);
lo = TCG_TMP3;
/* FALLTHRU */
case MO_32:
@ -1539,9 +1532,9 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0);
tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4);
} else {
tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi);
tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi, 0);
tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0);
tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo);
tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo, 0);
tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4);
}
break;
@ -1946,10 +1939,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_bswap16(s, a0, a1, a2);
break;
case INDEX_op_bswap32_i32:
tcg_out_bswap32(s, a0, a1);
tcg_out_bswap32(s, a0, a1, 0);
break;
case INDEX_op_bswap32_i64:
tcg_out_bswap32u(s, a0, a1);
tcg_out_bswap32(s, a0, a1, a2);
break;
case INDEX_op_bswap64_i64:
tcg_out_bswap64(s, a0, a1);