target/s390x: Use tcg_gen_atomic_cmpxchg_i128 for CDSG
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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2b91240f95
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1fcd84fa0d
@ -35,8 +35,6 @@ DEF_HELPER_3(cxgb, i128, env, s64, i32)
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DEF_HELPER_3(celgb, i64, env, i64, i32)
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DEF_HELPER_3(celgb, i64, env, i64, i32)
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DEF_HELPER_3(cdlgb, i64, env, i64, i32)
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DEF_HELPER_3(cdlgb, i64, env, i64, i32)
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DEF_HELPER_3(cxlgb, i128, env, i64, i32)
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DEF_HELPER_3(cxlgb, i128, env, i64, i32)
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DEF_HELPER_4(cdsg, void, env, i64, i32, i32)
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DEF_HELPER_4(cdsg_parallel, void, env, i64, i32, i32)
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DEF_HELPER_4(csst, i32, env, i32, i64, i64)
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DEF_HELPER_4(csst, i32, env, i32, i64, i64)
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DEF_HELPER_4(csst_parallel, i32, env, i32, i64, i64)
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DEF_HELPER_4(csst_parallel, i32, env, i32, i64, i64)
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DEF_HELPER_FLAGS_3(aeb, TCG_CALL_NO_WG, i64, env, i64, i64)
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DEF_HELPER_FLAGS_3(aeb, TCG_CALL_NO_WG, i64, env, i64, i64)
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@ -276,7 +276,7 @@
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/* COMPARE DOUBLE AND SWAP */
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/* COMPARE DOUBLE AND SWAP */
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D(0xbb00, CDS, RS_a, Z, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_TEUQ)
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D(0xbb00, CDS, RS_a, Z, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_TEUQ)
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D(0xeb31, CDSY, RSY_a, LD, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_TEUQ)
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D(0xeb31, CDSY, RSY_a, LD, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_TEUQ)
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C(0xeb3e, CDSG, RSY_a, Z, 0, 0, 0, 0, cdsg, 0)
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C(0xeb3e, CDSG, RSY_a, Z, la2, r3_D64, 0, r1_D64, cdsg, 0)
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/* COMPARE AND SWAP AND STORE */
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/* COMPARE AND SWAP AND STORE */
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C(0xc802, CSST, SSF, CASS, la1, a2, 0, 0, csst, 0)
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C(0xc802, CSST, SSF, CASS, la1, a2, 0, 0, csst, 0)
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@ -1771,58 +1771,6 @@ uint32_t HELPER(trXX)(CPUS390XState *env, uint32_t r1, uint32_t r2,
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return cc;
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return cc;
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}
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}
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void HELPER(cdsg)(CPUS390XState *env, uint64_t addr,
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uint32_t r1, uint32_t r3)
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{
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uintptr_t ra = GETPC();
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Int128 cmpv = int128_make128(env->regs[r1 + 1], env->regs[r1]);
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Int128 newv = int128_make128(env->regs[r3 + 1], env->regs[r3]);
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Int128 oldv;
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uint64_t oldh, oldl;
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bool fail;
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check_alignment(env, addr, 16, ra);
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oldh = cpu_ldq_data_ra(env, addr + 0, ra);
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oldl = cpu_ldq_data_ra(env, addr + 8, ra);
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oldv = int128_make128(oldl, oldh);
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fail = !int128_eq(oldv, cmpv);
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if (fail) {
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newv = oldv;
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}
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cpu_stq_data_ra(env, addr + 0, int128_gethi(newv), ra);
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cpu_stq_data_ra(env, addr + 8, int128_getlo(newv), ra);
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env->cc_op = fail;
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env->regs[r1] = int128_gethi(oldv);
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env->regs[r1 + 1] = int128_getlo(oldv);
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}
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void HELPER(cdsg_parallel)(CPUS390XState *env, uint64_t addr,
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uint32_t r1, uint32_t r3)
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{
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uintptr_t ra = GETPC();
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Int128 cmpv = int128_make128(env->regs[r1 + 1], env->regs[r1]);
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Int128 newv = int128_make128(env->regs[r3 + 1], env->regs[r3]);
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int mem_idx;
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MemOpIdx oi;
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Int128 oldv;
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bool fail;
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assert(HAVE_CMPXCHG128);
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mem_idx = cpu_mmu_index(env, false);
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oi = make_memop_idx(MO_TE | MO_128 | MO_ALIGN, mem_idx);
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oldv = cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra);
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fail = !int128_eq(oldv, cmpv);
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env->cc_op = fail;
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env->regs[r1] = int128_gethi(oldv);
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env->regs[r1 + 1] = int128_getlo(oldv);
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}
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static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1,
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static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1,
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uint64_t a2, bool parallel)
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uint64_t a2, bool parallel)
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{
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{
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@ -2224,31 +2224,25 @@ static DisasJumpType op_cs(DisasContext *s, DisasOps *o)
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static DisasJumpType op_cdsg(DisasContext *s, DisasOps *o)
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static DisasJumpType op_cdsg(DisasContext *s, DisasOps *o)
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{
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{
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int r1 = get_field(s, r1);
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int r1 = get_field(s, r1);
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int r3 = get_field(s, r3);
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int d2 = get_field(s, d2);
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int b2 = get_field(s, b2);
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DisasJumpType ret = DISAS_NEXT;
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TCGv_i64 addr;
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TCGv_i32 t_r1, t_r3;
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/* Note that R1:R1+1 = expected value and R3:R3+1 = new value. */
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o->out_128 = tcg_temp_new_i128();
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addr = get_address(s, 0, b2, d2);
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tcg_gen_concat_i64_i128(o->out_128, regs[r1 + 1], regs[r1]);
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t_r1 = tcg_const_i32(r1);
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t_r3 = tcg_const_i32(r3);
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if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
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gen_helper_cdsg(cpu_env, addr, t_r1, t_r3);
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} else if (HAVE_CMPXCHG128) {
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gen_helper_cdsg_parallel(cpu_env, addr, t_r1, t_r3);
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} else {
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gen_helper_exit_atomic(cpu_env);
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ret = DISAS_NORETURN;
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}
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tcg_temp_free_i64(addr);
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tcg_temp_free_i32(t_r1);
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tcg_temp_free_i32(t_r3);
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set_cc_static(s);
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/* Note out (R1:R1+1) = expected value and in2 (R3:R3+1) = new value. */
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return ret;
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tcg_gen_atomic_cmpxchg_i128(o->out_128, o->addr1, o->out_128, o->in2_128,
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get_mem_index(s), MO_BE | MO_128 | MO_ALIGN);
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/*
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* Extract result into cc_dst:cc_src, compare vs the expected value
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* in the as yet unmodified input registers, then update CC_OP.
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*/
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tcg_gen_extr_i128_i64(cc_src, cc_dst, o->out_128);
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tcg_gen_xor_i64(cc_dst, cc_dst, regs[r1]);
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tcg_gen_xor_i64(cc_src, cc_src, regs[r1 + 1]);
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tcg_gen_or_i64(cc_dst, cc_dst, cc_src);
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set_cc_nz_u64(s, cc_dst);
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return DISAS_NEXT;
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}
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}
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static DisasJumpType op_csst(DisasContext *s, DisasOps *o)
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static DisasJumpType op_csst(DisasContext *s, DisasOps *o)
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@ -5488,6 +5482,13 @@ static void wout_r1_D32(DisasContext *s, DisasOps *o)
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}
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}
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#define SPEC_wout_r1_D32 SPEC_r1_even
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#define SPEC_wout_r1_D32 SPEC_r1_even
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static void wout_r1_D64(DisasContext *s, DisasOps *o)
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{
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int r1 = get_field(s, r1);
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tcg_gen_extr_i128_i64(regs[r1 + 1], regs[r1], o->out_128);
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}
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#define SPEC_wout_r1_D64 SPEC_r1_even
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static void wout_r3_P32(DisasContext *s, DisasOps *o)
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static void wout_r3_P32(DisasContext *s, DisasOps *o)
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{
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{
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int r3 = get_field(s, r3);
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int r3 = get_field(s, r3);
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@ -5935,6 +5936,14 @@ static void in2_r3(DisasContext *s, DisasOps *o)
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}
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}
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#define SPEC_in2_r3 0
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#define SPEC_in2_r3 0
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static void in2_r3_D64(DisasContext *s, DisasOps *o)
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{
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int r3 = get_field(s, r3);
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o->in2_128 = tcg_temp_new_i128();
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tcg_gen_concat_i64_i128(o->in2_128, regs[r3 + 1], regs[r3]);
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}
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#define SPEC_in2_r3_D64 SPEC_r3_even
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static void in2_r3_sr32(DisasContext *s, DisasOps *o)
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static void in2_r3_sr32(DisasContext *s, DisasOps *o)
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{
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{
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o->in2 = tcg_temp_new_i64();
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o->in2 = tcg_temp_new_i64();
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