mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

tcg-aarch64: Support muluh, mulsh

Browse Source 
Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
This commit is contained in:
Richard Henderson 2013-08-14 15:03:27 -07:00
parent c6e929e784
commit 1fcc9ddfb3
2 changed files with 14 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
tcg/aarch64/tcg-target.c
View File

@ -311,6 +311,8 @@ typedef enum {
I3508_LSRV = 0x1ac02400,
I3508_ASRV = 0x1ac02800,
I3508_RORV = 0x1ac02c00,
I3508_SMULH = 0x9b407c00,
I3508_UMULH = 0x9bc07c00,
/* Logical shifted register instructions (without a shift). */
I3510_AND = 0x0a000000,
@ -1565,6 +1567,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
args[5], const_args[4], const_args[5], true);
break;
case INDEX_op_muluh_i64:
tcg_out_insn(s, 3508, UMULH, TCG_TYPE_I64, a0, a1, a2);
break;
case INDEX_op_mulsh_i64:
tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2);
break;
case INDEX_op_mov_i64:
case INDEX_op_mov_i32:
case INDEX_op_movi_i64:
@ -1694,6 +1703,9 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rwA", "rwMZ" } },
{ INDEX_op_sub2_i64, { "r", "r", "rZ", "rZ", "rA", "rMZ" } },
{ INDEX_op_muluh_i64, { "r", "r", "r" } },
{ INDEX_op_mulsh_i64, { "r", "r", "r" } },
{ -1 },
};

4
tcg/aarch64/tcg-target.h
View File

@ -89,8 +89,8 @@ typedef enum {
#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 0
#define TCG_TARGET_HAS_muls2_i64 0
#define TCG_TARGET_HAS_muluh_i64 0
#define TCG_TARGET_HAS_mulsh_i64 0
#define TCG_TARGET_HAS_muluh_i64 1
#define TCG_TARGET_HAS_mulsh_i64 1
enum {
TCG_AREG0 = TCG_REG_X19,