target-arm: A64: Add integer ops from SIMD 3-same group
Add some of the integer operations in the SIMD 3-same group: specifically, the comparisons, addition and subtraction. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Peter Maydell
parent
956d272eb2
commit
1f8a73af12
@ -72,6 +72,9 @@ typedef struct AArch64DecodeTable {
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AArch64DecodeFn *disas_fn;
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} AArch64DecodeTable;
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/* Function prototype for gen_ functions for calling Neon helpers */
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typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
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/* initialize TCG globals. */
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void a64_translate_init(void)
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{
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@ -787,6 +790,25 @@ static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx,
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}
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}
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static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,
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int destidx, int element, TCGMemOp memop)
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{
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int vect_off = vec_reg_offset(destidx, element, memop & MO_SIZE);
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switch (memop) {
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case MO_8:
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tcg_gen_st8_i32(tcg_src, cpu_env, vect_off);
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break;
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case MO_16:
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tcg_gen_st16_i32(tcg_src, cpu_env, vect_off);
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break;
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case MO_32:
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tcg_gen_st_i32(tcg_src, cpu_env, vect_off);
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break;
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default:
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g_assert_not_reached();
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}
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}
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/* Clear the high 64 bits of a 128 bit vector (in general non-quad
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* vector ops all need to do this).
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*/
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@ -6012,7 +6034,148 @@ static void disas_simd_3same_float(DisasContext *s, uint32_t insn)
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/* Integer op subgroup of C3.6.16. */
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static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
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{
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unsupported_encoding(s, insn);
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int is_q = extract32(insn, 30, 1);
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int u = extract32(insn, 29, 1);
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int size = extract32(insn, 22, 2);
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int opcode = extract32(insn, 11, 5);
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int rm = extract32(insn, 16, 5);
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int rn = extract32(insn, 5, 5);
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int rd = extract32(insn, 0, 5);
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int pass;
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switch (opcode) {
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case 0x13: /* MUL, PMUL */
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if (u && size != 0) {
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unallocated_encoding(s);
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return;
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}
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/* fall through */
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case 0x0: /* SHADD, UHADD */
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case 0x2: /* SRHADD, URHADD */
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case 0x4: /* SHSUB, UHSUB */
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case 0xc: /* SMAX, UMAX */
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case 0xd: /* SMIN, UMIN */
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case 0xe: /* SABD, UABD */
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case 0xf: /* SABA, UABA */
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case 0x12: /* MLA, MLS */
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if (size == 3) {
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unallocated_encoding(s);
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return;
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}
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unsupported_encoding(s, insn);
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return;
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case 0x1: /* SQADD */
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case 0x5: /* SQSUB */
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case 0x8: /* SSHL, USHL */
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case 0x9: /* SQSHL, UQSHL */
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case 0xa: /* SRSHL, URSHL */
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case 0xb: /* SQRSHL, UQRSHL */
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if (size == 3 && !is_q) {
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unallocated_encoding(s);
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return;
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}
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unsupported_encoding(s, insn);
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return;
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case 0x16: /* SQDMULH, SQRDMULH */
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if (size == 0 || size == 3) {
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unallocated_encoding(s);
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return;
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}
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unsupported_encoding(s, insn);
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return;
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default:
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if (size == 3 && !is_q) {
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unallocated_encoding(s);
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return;
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}
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break;
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}
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if (size == 3) {
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for (pass = 0; pass < (is_q ? 2 : 1); pass++) {
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TCGv_i64 tcg_op1 = tcg_temp_new_i64();
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TCGv_i64 tcg_op2 = tcg_temp_new_i64();
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TCGv_i64 tcg_res = tcg_temp_new_i64();
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read_vec_element(s, tcg_op1, rn, pass, MO_64);
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read_vec_element(s, tcg_op2, rm, pass, MO_64);
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handle_3same_64(s, opcode, u, tcg_res, tcg_op1, tcg_op2);
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write_vec_element(s, tcg_res, rd, pass, MO_64);
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tcg_temp_free_i64(tcg_res);
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tcg_temp_free_i64(tcg_op1);
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tcg_temp_free_i64(tcg_op2);
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}
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} else {
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for (pass = 0; pass < (is_q ? 4 : 2); pass++) {
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TCGv_i32 tcg_op1 = tcg_temp_new_i32();
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TCGv_i32 tcg_op2 = tcg_temp_new_i32();
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TCGv_i32 tcg_res = tcg_temp_new_i32();
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NeonGenTwoOpFn *genfn;
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read_vec_element_i32(s, tcg_op1, rn, pass, MO_32);
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read_vec_element_i32(s, tcg_op2, rm, pass, MO_32);
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switch (opcode) {
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case 0x6: /* CMGT, CMHI */
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{
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static NeonGenTwoOpFn * const fns[3][2] = {
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{ gen_helper_neon_cgt_s8, gen_helper_neon_cgt_u8 },
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{ gen_helper_neon_cgt_s16, gen_helper_neon_cgt_u16 },
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{ gen_helper_neon_cgt_s32, gen_helper_neon_cgt_u32 },
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};
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genfn = fns[size][u];
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break;
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}
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case 0x7: /* CMGE, CMHS */
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{
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static NeonGenTwoOpFn * const fns[3][2] = {
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{ gen_helper_neon_cge_s8, gen_helper_neon_cge_u8 },
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{ gen_helper_neon_cge_s16, gen_helper_neon_cge_u16 },
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{ gen_helper_neon_cge_s32, gen_helper_neon_cge_u32 },
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};
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genfn = fns[size][u];
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break;
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}
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case 0x10: /* ADD, SUB */
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{
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static NeonGenTwoOpFn * const fns[3][2] = {
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{ gen_helper_neon_add_u8, gen_helper_neon_sub_u8 },
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{ gen_helper_neon_add_u16, gen_helper_neon_sub_u16 },
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{ tcg_gen_add_i32, tcg_gen_sub_i32 },
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};
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genfn = fns[size][u];
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break;
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}
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case 0x11: /* CMTST, CMEQ */
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{
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static NeonGenTwoOpFn * const fns[3][2] = {
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{ gen_helper_neon_tst_u8, gen_helper_neon_ceq_u8 },
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{ gen_helper_neon_tst_u16, gen_helper_neon_ceq_u16 },
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{ gen_helper_neon_tst_u32, gen_helper_neon_ceq_u32 },
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};
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genfn = fns[size][u];
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break;
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}
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default:
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g_assert_not_reached();
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}
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genfn(tcg_res, tcg_op1, tcg_op2);
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write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
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tcg_temp_free_i32(tcg_res);
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tcg_temp_free_i32(tcg_op1);
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tcg_temp_free_i32(tcg_op2);
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}
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}
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if (!is_q) {
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clear_vec_high(s, rd);
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}
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}
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/* C3.6.16 AdvSIMD three same
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