hw/arm/aspeed_ast27x0: Avoid hardcoded '256' in IRQ calculation
When calculating the index into the GIC's GPIO array for per-CPU interrupts, we have to start with the number of SPIs. The code currently hard-codes this to 'NUM_IRQS = 256'. However the number of SPIs is set separately and implicitly by the value of AST2700_MAX_IRQ, which is the number of SPIs plus 32 (since it is what we set the GIC num-irq property to). Define AST2700_MAX_IRQ as the total number of SPIs; this brings AST2700 into line with AST2600, which defines AST2600_MAX_IRQ as the number of SPIs not including the 32 internal interrupts. We can then use AST2700_MAX_IRQ instead of the hardcoded 256. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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@ -66,7 +66,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
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[ASPEED_DEV_GPIO] = 0x14C0B000,
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};
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#define AST2700_MAX_IRQ 288
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#define AST2700_MAX_IRQ 256
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/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
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static const int aspeed_soc_ast2700_irqmap[] = {
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@ -403,7 +403,7 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp)
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gicdev = DEVICE(&a->gic);
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qdev_prop_set_uint32(gicdev, "revision", 3);
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qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus);
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qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ);
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qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ + GIC_INTERNAL);
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redist_region_count = qlist_new();
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qlist_append_int(redist_region_count, sc->num_cpus);
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@ -417,8 +417,7 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp)
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for (i = 0; i < sc->num_cpus; i++) {
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DeviceState *cpudev = DEVICE(&a->cpu[i]);
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int NUM_IRQS = 256;
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int intidbase = NUM_IRQS + i * GIC_INTERNAL;
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int intidbase = AST2700_MAX_IRQ + i * GIC_INTERNAL;
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const int timer_irq[] = {
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[GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
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