target/arm: Convert SUQADD, USQADD to decodetree
These are faux 2-operand instructions, reading from rd. Sort them next to the other three-operand same insns for clarity. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -45,6 +45,7 @@
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@rrr_sd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_sd
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@rrr_hsd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_hsd
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@rrr_e ........ esz:2 . rm:5 ...... rn:5 rd:5 &rrr_e
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@r2r_e ........ esz:2 . ..... ...... rm:5 rd:5 &rrr_e rn=%rd
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@rrx_h ........ .. .. rm:4 .... . . rn:5 rd:5 &rrx_e esz=1 idx=%hlm
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@rrx_s ........ .. . rm:5 .... . . rn:5 rd:5 &rrx_e esz=2 idx=%hl
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@ -60,6 +61,7 @@
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@qrrr_h . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=1
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@qrrr_sd . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=%esz_sd
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@qrrr_e . q:1 ...... esz:2 . rm:5 ...... rn:5 rd:5 &qrrr_e
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@qr2r_e . q:1 ...... esz:2 . ..... ...... rm:5 rd:5 &qrrr_e rn=%rd
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@qrrx_h . q:1 .. .... .. .. rm:4 .... . . rn:5 rd:5 \
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&qrrx_e esz=1 idx=%hlm
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@ -750,6 +752,9 @@ UQADD_s 0111 1110 ..1 ..... 00001 1 ..... ..... @rrr_e
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SQSUB_s 0101 1110 ..1 ..... 00101 1 ..... ..... @rrr_e
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UQSUB_s 0111 1110 ..1 ..... 00101 1 ..... ..... @rrr_e
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SUQADD_s 0101 1110 ..1 00000 00111 0 ..... ..... @r2r_e
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USQADD_s 0111 1110 ..1 00000 00111 0 ..... ..... @r2r_e
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### Advanced SIMD scalar pairwise
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FADDP_s 0101 1110 0011 0000 1101 10 ..... ..... @rr_h
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@ -868,6 +873,9 @@ UQADD_v 0.10 1110 ..1 ..... 00001 1 ..... ..... @qrrr_e
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SQSUB_v 0.00 1110 ..1 ..... 00101 1 ..... ..... @qrrr_e
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UQSUB_v 0.10 1110 ..1 ..... 00101 1 ..... ..... @qrrr_e
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SUQADD_v 0.00 1110 ..1 00000 00111 0 ..... ..... @qr2r_e
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USQADD_v 0.10 1110 ..1 00000 00111 0 ..... ..... @qr2r_e
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### Advanced SIMD scalar x indexed element
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FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h
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@ -5096,6 +5096,8 @@ TRANS(SQADD_s, do_satacc_s, a, MO_SIGN, MO_SIGN, gen_sqadd_bhs, gen_sqadd_d)
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TRANS(SQSUB_s, do_satacc_s, a, MO_SIGN, MO_SIGN, gen_sqsub_bhs, gen_sqsub_d)
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TRANS(UQADD_s, do_satacc_s, a, 0, 0, gen_uqadd_bhs, gen_uqadd_d)
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TRANS(UQSUB_s, do_satacc_s, a, 0, 0, gen_uqsub_bhs, gen_uqsub_d)
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TRANS(SUQADD_s, do_satacc_s, a, MO_SIGN, 0, gen_suqadd_bhs, gen_suqadd_d)
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TRANS(USQADD_s, do_satacc_s, a, 0, MO_SIGN, gen_usqadd_bhs, gen_usqadd_d)
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static bool do_fp3_vector(DisasContext *s, arg_qrrr_e *a,
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gen_helper_gvec_3_ptr * const fns[3])
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@ -5339,6 +5341,8 @@ TRANS(SQADD_v, do_gvec_fn3, a, gen_gvec_sqadd_qc)
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TRANS(UQADD_v, do_gvec_fn3, a, gen_gvec_uqadd_qc)
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TRANS(SQSUB_v, do_gvec_fn3, a, gen_gvec_sqsub_qc)
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TRANS(UQSUB_v, do_gvec_fn3, a, gen_gvec_uqsub_qc)
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TRANS(SUQADD_v, do_gvec_fn3, a, gen_gvec_suqadd_qc)
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TRANS(USQADD_v, do_gvec_fn3, a, gen_gvec_usqadd_qc)
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/*
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* Advanced SIMD scalar/vector x indexed element
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@ -10009,48 +10013,6 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
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clear_vec_high(s, is_q, rd);
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}
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/* Remaining saturating accumulating ops */
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static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
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bool is_q, unsigned size, int rn, int rd)
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{
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TCGv_i64 res, qc, a, b;
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if (!is_scalar) {
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gen_gvec_fn3(s, is_q, rd, rd, rn,
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is_u ? gen_gvec_usqadd_qc : gen_gvec_suqadd_qc, size);
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return;
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}
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res = tcg_temp_new_i64();
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qc = tcg_temp_new_i64();
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a = tcg_temp_new_i64();
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b = tcg_temp_new_i64();
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/* Read and extend scalar inputs to 64-bits. */
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read_vec_element(s, a, rd, 0, size | (is_u ? 0 : MO_SIGN));
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read_vec_element(s, b, rn, 0, size | (is_u ? MO_SIGN : 0));
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tcg_gen_ld_i64(qc, tcg_env, offsetof(CPUARMState, vfp.qc));
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if (size == MO_64) {
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if (is_u) {
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gen_usqadd_d(res, qc, a, b);
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} else {
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gen_suqadd_d(res, qc, a, b);
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}
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} else {
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if (is_u) {
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gen_usqadd_bhs(res, qc, a, b, size);
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} else {
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gen_suqadd_bhs(res, qc, a, b, size);
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/* Truncate signed 64-bit result for writeback. */
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tcg_gen_ext_i64(res, res, size);
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}
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}
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write_fp_dreg(s, rd, res);
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tcg_gen_st_i64(qc, tcg_env, offsetof(CPUARMState, vfp.qc));
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}
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/* AdvSIMD scalar two reg misc
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* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
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* +-----+---+-----------+------+-----------+--------+-----+------+------+
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@ -10070,12 +10032,6 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
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TCGv_ptr tcg_fpstatus;
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switch (opcode) {
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case 0x3: /* USQADD / SUQADD*/
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if (!fp_access_check(s)) {
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return;
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}
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handle_2misc_satacc(s, true, u, false, size, rn, rd);
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return;
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case 0x7: /* SQABS / SQNEG */
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break;
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case 0xa: /* CMLT */
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@ -10175,6 +10131,7 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
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}
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break;
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default:
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case 0x3: /* USQADD / SUQADD */
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unallocated_encoding(s);
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return;
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}
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@ -11662,16 +11619,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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return;
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}
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break;
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case 0x3: /* SUQADD, USQADD */
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if (size == 3 && !is_q) {
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unallocated_encoding(s);
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return;
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}
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if (!fp_access_check(s)) {
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return;
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}
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handle_2misc_satacc(s, false, u, is_q, size, rn, rd);
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return;
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case 0x7: /* SQABS, SQNEG */
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if (size == 3 && !is_q) {
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unallocated_encoding(s);
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@ -11846,6 +11793,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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break;
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}
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default:
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case 0x3: /* SUQADD, USQADD */
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unallocated_encoding(s);
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return;
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}
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