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ne2000: convert to memory API

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Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Avi Kivity 2011-08-08 16:09:18 +03:00 committed by Anthony Liguori
parent 23c5e4cab2
commit 1ec4e1ddc9
3 changed files with 59 additions and 41 deletions
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13
hw/ne2000-isa.c
View File

@ -27,6 +27,7 @@
#include "qdev.h"
#include "net.h"
#include "ne2000.h"
#include "exec-memory.h"
typedef struct ISANE2000State {
ISADevice dev;
@ -66,19 +67,11 @@ static int isa_ne2000_initfn(ISADevice *dev)
ISANE2000State *isa = DO_UPCAST(ISANE2000State, dev, dev);
NE2000State *s = &isa->ne2000;
register_ioport_write(isa->iobase, 16, 1, ne2000_ioport_write, s);
register_ioport_read(isa->iobase, 16, 1, ne2000_ioport_read, s);
ne2000_setup_io(s, 0x20);
isa_init_ioport_range(dev, isa->iobase, 16);
register_ioport_write(isa->iobase + 0x10, 1, 1, ne2000_asic_ioport_write, s);
register_ioport_read(isa->iobase + 0x10, 1, 1, ne2000_asic_ioport_read, s);
register_ioport_write(isa->iobase + 0x10, 2, 2, ne2000_asic_ioport_write, s);
register_ioport_read(isa->iobase + 0x10, 2, 2, ne2000_asic_ioport_read, s);
isa_init_ioport_range(dev, isa->iobase + 0x10, 2);
register_ioport_write(isa->iobase + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
register_ioport_read(isa->iobase + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
isa_init_ioport(dev, isa->iobase + 0x1f);
memory_region_add_subregion(get_system_io(), isa->iobase, &s->io);
isa_init_irq(dev, &s->irq, isa->isairq);

79
hw/ne2000.c
View File

@ -297,7 +297,7 @@ ssize_t ne2000_receive(VLANClientState *nc, const uint8_t *buf, size_t size_)
return size_;
}
void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
NE2000State *s = opaque;
int offset, page, index;
@ -394,7 +394,7 @@ void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
}
}
uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
{
NE2000State *s = opaque;
int offset, page, ret;
@ -544,7 +544,7 @@ static inline void ne2000_dma_update(NE2000State *s, int len)
}
}
void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
NE2000State *s = opaque;
@ -564,7 +564,7 @@ void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
}
}
uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
{
NE2000State *s = opaque;
int ret;
@ -612,12 +612,12 @@ static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr)
return ret;
}
void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
/* nothing to do (end of reset pulse) */
}
uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
{
NE2000State *s = opaque;
ne2000_reset(s);
@ -676,27 +676,55 @@ static const VMStateDescription vmstate_pci_ne2000 = {
}
};
static uint64_t ne2000_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
NE2000State *s = opaque;
if (addr < 0x10 && size == 1) {
return ne2000_ioport_read(s, addr);
} else if (addr == 0x10) {
if (size <= 2) {
return ne2000_asic_ioport_read(s, addr);
} else {
return ne2000_asic_ioport_readl(s, addr);
}
} else if (addr == 0x1f && size == 1) {
return ne2000_reset_ioport_read(s, addr);
}
return ((uint64_t)1 << (size * 8)) - 1;
}
static void ne2000_write(void *opaque, target_phys_addr_t addr,
uint64_t data, unsigned size)
{
NE2000State *s = opaque;
if (addr < 0x10 && size == 1) {
return ne2000_ioport_write(s, addr, data);
} else if (addr == 0x10) {
if (size <= 2) {
return ne2000_asic_ioport_write(s, addr, data);
} else {
return ne2000_asic_ioport_writel(s, addr, data);
}
} else if (addr == 0x1f && size == 1) {
return ne2000_reset_ioport_write(s, addr, data);
}
}
static const MemoryRegionOps ne2000_ops = {
.read = ne2000_read,
.write = ne2000_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
/***********************************************************/
/* PCI NE2000 definitions */
static void ne2000_map(PCIDevice *pci_dev, int region_num,
pcibus_t addr, pcibus_t size, int type)
void ne2000_setup_io(NE2000State *s, unsigned size)
{
PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
NE2000State *s = &d->ne2000;
register_ioport_write(addr, 16, 1, ne2000_ioport_write, s);
register_ioport_read(addr, 16, 1, ne2000_ioport_read, s);
register_ioport_write(addr + 0x10, 1, 1, ne2000_asic_ioport_write, s);
register_ioport_read(addr + 0x10, 1, 1, ne2000_asic_ioport_read, s);
register_ioport_write(addr + 0x10, 2, 2, ne2000_asic_ioport_write, s);
register_ioport_read(addr + 0x10, 2, 2, ne2000_asic_ioport_read, s);
register_ioport_write(addr + 0x10, 4, 4, ne2000_asic_ioport_writel, s);
register_ioport_read(addr + 0x10, 4, 4, ne2000_asic_ioport_readl, s);
register_ioport_write(addr + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
register_ioport_read(addr + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
memory_region_init_io(&s->io, &ne2000_ops, s, "ne2000", size);
}
static void ne2000_cleanup(VLANClientState *nc)
@ -724,9 +752,9 @@ static int pci_ne2000_init(PCIDevice *pci_dev)
/* TODO: RST# value should be 0. PCI spec 6.2.4 */
pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0
pci_register_bar(&d->dev, 0, 0x100,
PCI_BASE_ADDRESS_SPACE_IO, ne2000_map);
s = &d->ne2000;
ne2000_setup_io(s, 0x100);
pci_register_bar_region(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
s->irq = d->dev.irq[0];
qemu_macaddr_default_if_unset(&s->c.macaddr);
@ -754,6 +782,7 @@ static int pci_ne2000_exit(PCIDevice *pci_dev)
PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
NE2000State *s = &d->ne2000;
memory_region_destroy(&s->io);
qemu_del_vlan_client(&s->nic->nc);
return 0;
}

8
hw/ne2000.h
View File

@ -4,6 +4,7 @@
#define NE2000_MEM_SIZE NE2000_PMEM_END
typedef struct NE2000State {
MemoryRegion io;
uint8_t cmd;
uint32_t start;
uint32_t stop;
@ -27,12 +28,7 @@ typedef struct NE2000State {
uint8_t mem[NE2000_MEM_SIZE];
} NE2000State;
void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val);
uint32_t ne2000_ioport_read(void *opaque, uint32_t addr);
void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val);
uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr);
void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val);
uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr);
void ne2000_setup_io(NE2000State *s, unsigned size);
extern const VMStateDescription vmstate_ne2000;
void ne2000_reset(NE2000State *s);
int ne2000_can_receive(VLANClientState *vc);