target/arm: Convert to HAVE_CMPXCHG128
Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
e1ed709fbe
commit
1ec182c333
@ -30,6 +30,7 @@
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#include "exec/exec-all.h"
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#include "exec/cpu_ldst.h"
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#include "qemu/int128.h"
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#include "qemu/atomic128.h"
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#include "tcg.h"
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#include "fpu/softfloat.h"
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#include <zlib.h> /* For crc32 */
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@ -509,189 +510,195 @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, uint32_t bytes)
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return crc32c(acc, buf, bytes) ^ 0xffffffff;
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}
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/* Returns 0 on success; 1 otherwise. */
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static uint64_t do_paired_cmpxchg64_le(CPUARMState *env, uint64_t addr,
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uint64_t new_lo, uint64_t new_hi,
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bool parallel, uintptr_t ra)
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uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr,
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uint64_t new_lo, uint64_t new_hi)
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{
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Int128 oldv, cmpv, newv;
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Int128 cmpv = int128_make128(env->exclusive_val, env->exclusive_high);
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Int128 newv = int128_make128(new_lo, new_hi);
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Int128 oldv;
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uintptr_t ra = GETPC();
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uint64_t o0, o1;
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bool success;
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cmpv = int128_make128(env->exclusive_val, env->exclusive_high);
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newv = int128_make128(new_lo, new_hi);
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if (parallel) {
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#ifndef CONFIG_ATOMIC128
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cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
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#else
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int mem_idx = cpu_mmu_index(env, false);
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TCGMemOpIdx oi = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
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oldv = helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra);
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success = int128_eq(oldv, cmpv);
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#endif
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} else {
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uint64_t o0, o1;
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#ifdef CONFIG_USER_ONLY
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/* ??? Enforce alignment. */
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uint64_t *haddr = g2h(addr);
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/* ??? Enforce alignment. */
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uint64_t *haddr = g2h(addr);
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helper_retaddr = ra;
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o0 = ldq_le_p(haddr + 0);
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o1 = ldq_le_p(haddr + 1);
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oldv = int128_make128(o0, o1);
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helper_retaddr = ra;
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o0 = ldq_le_p(haddr + 0);
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o1 = ldq_le_p(haddr + 1);
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oldv = int128_make128(o0, o1);
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success = int128_eq(oldv, cmpv);
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if (success) {
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stq_le_p(haddr + 0, int128_getlo(newv));
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stq_le_p(haddr + 1, int128_gethi(newv));
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}
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helper_retaddr = 0;
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#else
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int mem_idx = cpu_mmu_index(env, false);
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TCGMemOpIdx oi0 = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
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TCGMemOpIdx oi1 = make_memop_idx(MO_LEQ, mem_idx);
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o0 = helper_le_ldq_mmu(env, addr + 0, oi0, ra);
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o1 = helper_le_ldq_mmu(env, addr + 8, oi1, ra);
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oldv = int128_make128(o0, o1);
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success = int128_eq(oldv, cmpv);
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if (success) {
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helper_le_stq_mmu(env, addr + 0, int128_getlo(newv), oi1, ra);
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helper_le_stq_mmu(env, addr + 8, int128_gethi(newv), oi1, ra);
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}
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#endif
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success = int128_eq(oldv, cmpv);
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if (success) {
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stq_le_p(haddr + 0, int128_getlo(newv));
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stq_le_p(haddr + 1, int128_gethi(newv));
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}
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helper_retaddr = 0;
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#else
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int mem_idx = cpu_mmu_index(env, false);
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TCGMemOpIdx oi0 = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
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TCGMemOpIdx oi1 = make_memop_idx(MO_LEQ, mem_idx);
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o0 = helper_le_ldq_mmu(env, addr + 0, oi0, ra);
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o1 = helper_le_ldq_mmu(env, addr + 8, oi1, ra);
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oldv = int128_make128(o0, o1);
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success = int128_eq(oldv, cmpv);
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if (success) {
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helper_le_stq_mmu(env, addr + 0, int128_getlo(newv), oi1, ra);
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helper_le_stq_mmu(env, addr + 8, int128_gethi(newv), oi1, ra);
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}
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#endif
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return !success;
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}
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uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr,
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uint64_t new_lo, uint64_t new_hi)
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{
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return do_paired_cmpxchg64_le(env, addr, new_lo, new_hi, false, GETPC());
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}
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uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMState *env, uint64_t addr,
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uint64_t new_lo, uint64_t new_hi)
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{
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return do_paired_cmpxchg64_le(env, addr, new_lo, new_hi, true, GETPC());
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}
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static uint64_t do_paired_cmpxchg64_be(CPUARMState *env, uint64_t addr,
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uint64_t new_lo, uint64_t new_hi,
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bool parallel, uintptr_t ra)
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{
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Int128 oldv, cmpv, newv;
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uintptr_t ra = GETPC();
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bool success;
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int mem_idx;
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TCGMemOpIdx oi;
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/* high and low need to be switched here because this is not actually a
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* 128bit store but two doublewords stored consecutively
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*/
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cmpv = int128_make128(env->exclusive_high, env->exclusive_val);
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newv = int128_make128(new_hi, new_lo);
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if (parallel) {
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#ifndef CONFIG_ATOMIC128
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if (!HAVE_CMPXCHG128) {
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cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
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#else
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int mem_idx = cpu_mmu_index(env, false);
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TCGMemOpIdx oi = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx);
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oldv = helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra);
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success = int128_eq(oldv, cmpv);
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#endif
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} else {
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uint64_t o0, o1;
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#ifdef CONFIG_USER_ONLY
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/* ??? Enforce alignment. */
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uint64_t *haddr = g2h(addr);
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helper_retaddr = ra;
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o1 = ldq_be_p(haddr + 0);
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o0 = ldq_be_p(haddr + 1);
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oldv = int128_make128(o0, o1);
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success = int128_eq(oldv, cmpv);
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if (success) {
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stq_be_p(haddr + 0, int128_gethi(newv));
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stq_be_p(haddr + 1, int128_getlo(newv));
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}
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helper_retaddr = 0;
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#else
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int mem_idx = cpu_mmu_index(env, false);
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TCGMemOpIdx oi0 = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx);
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TCGMemOpIdx oi1 = make_memop_idx(MO_BEQ, mem_idx);
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o1 = helper_be_ldq_mmu(env, addr + 0, oi0, ra);
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o0 = helper_be_ldq_mmu(env, addr + 8, oi1, ra);
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oldv = int128_make128(o0, o1);
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success = int128_eq(oldv, cmpv);
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if (success) {
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helper_be_stq_mmu(env, addr + 0, int128_gethi(newv), oi1, ra);
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helper_be_stq_mmu(env, addr + 8, int128_getlo(newv), oi1, ra);
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}
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#endif
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}
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mem_idx = cpu_mmu_index(env, false);
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oi = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
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cmpv = int128_make128(env->exclusive_val, env->exclusive_high);
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newv = int128_make128(new_lo, new_hi);
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oldv = helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra);
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success = int128_eq(oldv, cmpv);
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return !success;
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}
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uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr,
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uint64_t new_lo, uint64_t new_hi)
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{
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return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, false, GETPC());
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/*
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* High and low need to be switched here because this is not actually a
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* 128bit store but two doublewords stored consecutively
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*/
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Int128 cmpv = int128_make128(env->exclusive_val, env->exclusive_high);
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Int128 newv = int128_make128(new_lo, new_hi);
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Int128 oldv;
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uintptr_t ra = GETPC();
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uint64_t o0, o1;
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bool success;
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#ifdef CONFIG_USER_ONLY
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/* ??? Enforce alignment. */
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uint64_t *haddr = g2h(addr);
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helper_retaddr = ra;
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o1 = ldq_be_p(haddr + 0);
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o0 = ldq_be_p(haddr + 1);
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oldv = int128_make128(o0, o1);
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success = int128_eq(oldv, cmpv);
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if (success) {
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stq_be_p(haddr + 0, int128_gethi(newv));
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stq_be_p(haddr + 1, int128_getlo(newv));
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}
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helper_retaddr = 0;
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#else
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int mem_idx = cpu_mmu_index(env, false);
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TCGMemOpIdx oi0 = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx);
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TCGMemOpIdx oi1 = make_memop_idx(MO_BEQ, mem_idx);
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o1 = helper_be_ldq_mmu(env, addr + 0, oi0, ra);
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o0 = helper_be_ldq_mmu(env, addr + 8, oi1, ra);
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oldv = int128_make128(o0, o1);
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success = int128_eq(oldv, cmpv);
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if (success) {
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helper_be_stq_mmu(env, addr + 0, int128_gethi(newv), oi1, ra);
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helper_be_stq_mmu(env, addr + 8, int128_getlo(newv), oi1, ra);
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}
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#endif
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return !success;
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}
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uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t addr,
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uint64_t new_lo, uint64_t new_hi)
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uint64_t new_lo, uint64_t new_hi)
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{
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return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, true, GETPC());
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Int128 oldv, cmpv, newv;
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uintptr_t ra = GETPC();
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bool success;
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int mem_idx;
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TCGMemOpIdx oi;
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if (!HAVE_CMPXCHG128) {
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cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
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}
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mem_idx = cpu_mmu_index(env, false);
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oi = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx);
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/*
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* High and low need to be switched here because this is not actually a
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* 128bit store but two doublewords stored consecutively
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*/
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cmpv = int128_make128(env->exclusive_high, env->exclusive_val);
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newv = int128_make128(new_hi, new_lo);
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oldv = helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra);
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success = int128_eq(oldv, cmpv);
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return !success;
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}
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/* Writes back the old data into Rs. */
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void HELPER(casp_le_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr,
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uint64_t new_lo, uint64_t new_hi)
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{
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uintptr_t ra = GETPC();
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#ifndef CONFIG_ATOMIC128
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cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
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#else
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Int128 oldv, cmpv, newv;
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uintptr_t ra = GETPC();
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int mem_idx;
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TCGMemOpIdx oi;
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if (!HAVE_CMPXCHG128) {
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cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
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}
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mem_idx = cpu_mmu_index(env, false);
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oi = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
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cmpv = int128_make128(env->xregs[rs], env->xregs[rs + 1]);
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newv = int128_make128(new_lo, new_hi);
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int mem_idx = cpu_mmu_index(env, false);
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TCGMemOpIdx oi = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
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oldv = helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra);
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env->xregs[rs] = int128_getlo(oldv);
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env->xregs[rs + 1] = int128_gethi(oldv);
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#endif
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}
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void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr,
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uint64_t new_hi, uint64_t new_lo)
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{
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uintptr_t ra = GETPC();
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#ifndef CONFIG_ATOMIC128
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cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
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#else
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Int128 oldv, cmpv, newv;
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uintptr_t ra = GETPC();
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int mem_idx;
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TCGMemOpIdx oi;
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if (!HAVE_CMPXCHG128) {
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cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
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}
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mem_idx = cpu_mmu_index(env, false);
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oi = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
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cmpv = int128_make128(env->xregs[rs + 1], env->xregs[rs]);
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newv = int128_make128(new_lo, new_hi);
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int mem_idx = cpu_mmu_index(env, false);
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TCGMemOpIdx oi = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
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oldv = helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra);
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env->xregs[rs + 1] = int128_getlo(oldv);
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env->xregs[rs] = int128_gethi(oldv);
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#endif
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}
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/*
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