hw/misc/omap_clk: Remove OMAP2-specifics
Remove the handling for all non-OMAP1 SoCs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240903160751.4100218-52-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
9bc092f19c
commit
1e932548b2
@ -35,9 +35,6 @@ struct clk {
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#define CLOCK_IN_OMAP730 (1 << 11)
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#define CLOCK_IN_OMAP1510 (1 << 12)
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#define CLOCK_IN_OMAP16XX (1 << 13)
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#define CLOCK_IN_OMAP242X (1 << 14)
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#define CLOCK_IN_OMAP243X (1 << 15)
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#define CLOCK_IN_OMAP343X (1 << 16)
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uint32_t flags;
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int id;
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@ -59,8 +56,7 @@ static struct clk xtal_osc12m = {
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static struct clk xtal_osc32k = {
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.name = "xtal_osc_32k",
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.rate = 32768,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
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CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
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};
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static struct clk ck_ref = {
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@ -507,449 +503,10 @@ static struct clk i2c_ick = {
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static struct clk clk32k = {
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.name = "clk32-kHz",
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.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
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ALWAYS_ENABLED,
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.parent = &xtal_osc32k,
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};
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static struct clk ref_clk = {
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.name = "ref_clk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
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.rate = 12000000, /* 12 MHz or 13 MHz or 19.2 MHz */
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/*.parent = sys.xtalin */
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};
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static struct clk apll_96m = {
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.name = "apll_96m",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
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.rate = 96000000,
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/*.parent = ref_clk */
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};
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static struct clk apll_54m = {
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.name = "apll_54m",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
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.rate = 54000000,
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/*.parent = ref_clk */
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};
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static struct clk sys_clk = {
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.name = "sys_clk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
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.rate = 32768,
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/*.parent = sys.xtalin */
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};
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static struct clk sleep_clk = {
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.name = "sleep_clk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
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.rate = 32768,
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/*.parent = sys.xtalin */
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};
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static struct clk dpll_ck = {
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.name = "dpll",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
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.parent = &ref_clk,
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};
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static struct clk dpll_x2_ck = {
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.name = "dpll_x2",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
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.parent = &ref_clk,
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};
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static struct clk wdt1_sys_clk = {
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.name = "wdt1_sys_clk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
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.rate = 32768,
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/*.parent = sys.xtalin */
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};
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static struct clk func_96m_clk = {
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.name = "func_96m_clk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.divisor = 1,
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.parent = &apll_96m,
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};
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static struct clk func_48m_clk = {
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.name = "func_48m_clk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.divisor = 2,
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.parent = &apll_96m,
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};
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static struct clk func_12m_clk = {
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.name = "func_12m_clk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.divisor = 8,
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.parent = &apll_96m,
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};
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static struct clk func_54m_clk = {
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.name = "func_54m_clk",
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.flags = CLOCK_IN_OMAP242X,
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.divisor = 1,
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.parent = &apll_54m,
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};
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static struct clk sys_clkout = {
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.name = "clkout",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &sys_clk,
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};
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static struct clk sys_clkout2 = {
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.name = "clkout2",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &sys_clk,
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};
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static struct clk core_clk = {
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.name = "core_clk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &dpll_x2_ck, /* Switchable between dpll_ck and clk32k */
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};
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static struct clk l3_clk = {
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.name = "l3_clk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &core_clk,
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};
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static struct clk core_l4_iclk = {
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.name = "core_l4_iclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &l3_clk,
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};
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static struct clk wu_l4_iclk = {
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.name = "wu_l4_iclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &l3_clk,
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};
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static struct clk core_l3_iclk = {
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.name = "core_l3_iclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &core_clk,
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};
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static struct clk core_l4_usb_clk = {
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.name = "core_l4_usb_clk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &l3_clk,
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};
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static struct clk wu_gpt1_clk = {
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.name = "wu_gpt1_clk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &sys_clk,
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};
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static struct clk wu_32k_clk = {
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.name = "wu_32k_clk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &sys_clk,
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};
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static struct clk uart1_fclk = {
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.name = "uart1_fclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &func_48m_clk,
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};
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static struct clk uart1_iclk = {
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.name = "uart1_iclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &core_l4_iclk,
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};
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static struct clk uart2_fclk = {
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.name = "uart2_fclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &func_48m_clk,
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};
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static struct clk uart2_iclk = {
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.name = "uart2_iclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &core_l4_iclk,
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};
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static struct clk uart3_fclk = {
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.name = "uart3_fclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &func_48m_clk,
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};
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static struct clk uart3_iclk = {
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.name = "uart3_iclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &core_l4_iclk,
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};
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static struct clk mpu_fclk = {
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.name = "mpu_fclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &core_clk,
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};
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static struct clk mpu_iclk = {
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.name = "mpu_iclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &core_clk,
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};
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static struct clk int_m_fclk = {
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.name = "int_m_fclk",
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.alias = "mpu_intc_fclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &core_clk,
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};
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static struct clk int_m_iclk = {
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.name = "int_m_iclk",
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.alias = "mpu_intc_iclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &core_clk,
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};
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static struct clk core_gpt2_clk = {
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.name = "core_gpt2_clk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &sys_clk,
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};
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static struct clk core_gpt3_clk = {
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.name = "core_gpt3_clk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &sys_clk,
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};
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static struct clk core_gpt4_clk = {
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.name = "core_gpt4_clk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &sys_clk,
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};
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static struct clk core_gpt5_clk = {
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.name = "core_gpt5_clk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &sys_clk,
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};
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static struct clk core_gpt6_clk = {
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.name = "core_gpt6_clk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &sys_clk,
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};
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static struct clk core_gpt7_clk = {
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.name = "core_gpt7_clk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &sys_clk,
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};
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static struct clk core_gpt8_clk = {
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.name = "core_gpt8_clk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &sys_clk,
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};
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static struct clk core_gpt9_clk = {
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.name = "core_gpt9_clk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &sys_clk,
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};
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static struct clk core_gpt10_clk = {
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.name = "core_gpt10_clk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &sys_clk,
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};
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static struct clk core_gpt11_clk = {
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.name = "core_gpt11_clk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &sys_clk,
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};
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static struct clk core_gpt12_clk = {
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.name = "core_gpt12_clk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &sys_clk,
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};
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static struct clk mcbsp1_clk = {
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.name = "mcbsp1_cg",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.divisor = 2,
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.parent = &func_96m_clk,
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};
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static struct clk mcbsp2_clk = {
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.name = "mcbsp2_cg",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.divisor = 2,
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.parent = &func_96m_clk,
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};
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static struct clk emul_clk = {
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.name = "emul_ck",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &func_54m_clk,
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};
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static struct clk sdma_fclk = {
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.name = "sdma_fclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &l3_clk,
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};
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static struct clk sdma_iclk = {
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.name = "sdma_iclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &core_l3_iclk, /* core_l4_iclk for the configuration port */
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};
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static struct clk i2c1_fclk = {
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.name = "i2c1.fclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &func_12m_clk,
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.divisor = 1,
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};
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static struct clk i2c1_iclk = {
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.name = "i2c1.iclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &core_l4_iclk,
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};
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static struct clk i2c2_fclk = {
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.name = "i2c2.fclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &func_12m_clk,
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.divisor = 1,
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};
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static struct clk i2c2_iclk = {
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.name = "i2c2.iclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &core_l4_iclk,
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};
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static struct clk gpio_dbclk[5] = {
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{
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.name = "gpio1_dbclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &wu_32k_clk,
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}, {
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.name = "gpio2_dbclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &wu_32k_clk,
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}, {
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.name = "gpio3_dbclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &wu_32k_clk,
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}, {
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.name = "gpio4_dbclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &wu_32k_clk,
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}, {
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.name = "gpio5_dbclk",
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.flags = CLOCK_IN_OMAP243X,
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.parent = &wu_32k_clk,
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},
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};
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static struct clk gpio_iclk = {
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.name = "gpio_iclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &wu_l4_iclk,
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};
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static struct clk mmc_fck = {
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.name = "mmc_fclk",
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.flags = CLOCK_IN_OMAP242X,
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.parent = &func_96m_clk,
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};
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static struct clk mmc_ick = {
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.name = "mmc_iclk",
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.flags = CLOCK_IN_OMAP242X,
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.parent = &core_l4_iclk,
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};
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static struct clk spi_fclk[3] = {
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{
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.name = "spi1_fclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &func_48m_clk,
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}, {
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.name = "spi2_fclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &func_48m_clk,
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}, {
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.name = "spi3_fclk",
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.flags = CLOCK_IN_OMAP243X,
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.parent = &func_48m_clk,
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},
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};
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static struct clk dss_clk[2] = {
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{
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.name = "dss_clk1",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &core_clk,
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}, {
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.name = "dss_clk2",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &sys_clk,
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},
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};
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static struct clk dss_54m_clk = {
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.name = "dss_54m_clk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &func_54m_clk,
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};
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static struct clk dss_l3_iclk = {
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.name = "dss_l3_iclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &core_l3_iclk,
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};
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static struct clk dss_l4_iclk = {
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.name = "dss_l4_iclk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &core_l4_iclk,
|
||||
};
|
||||
|
||||
static struct clk spi_iclk[3] = {
|
||||
{
|
||||
.name = "spi1_iclk",
|
||||
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
|
||||
.parent = &core_l4_iclk,
|
||||
}, {
|
||||
.name = "spi2_iclk",
|
||||
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
|
||||
.parent = &core_l4_iclk,
|
||||
}, {
|
||||
.name = "spi3_iclk",
|
||||
.flags = CLOCK_IN_OMAP243X,
|
||||
.parent = &core_l4_iclk,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk omapctrl_clk = {
|
||||
.name = "omapctrl_iclk",
|
||||
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
|
||||
/* XXX Should be in WKUP domain */
|
||||
.parent = &core_l4_iclk,
|
||||
};
|
||||
|
||||
static struct clk *onchip_clks[] = {
|
||||
/* OMAP 1 */
|
||||
|
||||
@ -1019,80 +576,6 @@ static struct clk *onchip_clks[] = {
|
||||
&i2c_fck,
|
||||
&i2c_ick,
|
||||
|
||||
/* OMAP 2 */
|
||||
|
||||
&ref_clk,
|
||||
&apll_96m,
|
||||
&apll_54m,
|
||||
&sys_clk,
|
||||
&sleep_clk,
|
||||
&dpll_ck,
|
||||
&dpll_x2_ck,
|
||||
&wdt1_sys_clk,
|
||||
&func_96m_clk,
|
||||
&func_48m_clk,
|
||||
&func_12m_clk,
|
||||
&func_54m_clk,
|
||||
&sys_clkout,
|
||||
&sys_clkout2,
|
||||
&core_clk,
|
||||
&l3_clk,
|
||||
&core_l4_iclk,
|
||||
&wu_l4_iclk,
|
||||
&core_l3_iclk,
|
||||
&core_l4_usb_clk,
|
||||
&wu_gpt1_clk,
|
||||
&wu_32k_clk,
|
||||
&uart1_fclk,
|
||||
&uart1_iclk,
|
||||
&uart2_fclk,
|
||||
&uart2_iclk,
|
||||
&uart3_fclk,
|
||||
&uart3_iclk,
|
||||
&mpu_fclk,
|
||||
&mpu_iclk,
|
||||
&int_m_fclk,
|
||||
&int_m_iclk,
|
||||
&core_gpt2_clk,
|
||||
&core_gpt3_clk,
|
||||
&core_gpt4_clk,
|
||||
&core_gpt5_clk,
|
||||
&core_gpt6_clk,
|
||||
&core_gpt7_clk,
|
||||
&core_gpt8_clk,
|
||||
&core_gpt9_clk,
|
||||
&core_gpt10_clk,
|
||||
&core_gpt11_clk,
|
||||
&core_gpt12_clk,
|
||||
&mcbsp1_clk,
|
||||
&mcbsp2_clk,
|
||||
&emul_clk,
|
||||
&sdma_fclk,
|
||||
&sdma_iclk,
|
||||
&i2c1_fclk,
|
||||
&i2c1_iclk,
|
||||
&i2c2_fclk,
|
||||
&i2c2_iclk,
|
||||
&gpio_dbclk[0],
|
||||
&gpio_dbclk[1],
|
||||
&gpio_dbclk[2],
|
||||
&gpio_dbclk[3],
|
||||
&gpio_iclk,
|
||||
&mmc_fck,
|
||||
&mmc_ick,
|
||||
&spi_fclk[0],
|
||||
&spi_iclk[0],
|
||||
&spi_fclk[1],
|
||||
&spi_iclk[1],
|
||||
&spi_fclk[2],
|
||||
&spi_iclk[2],
|
||||
&dss_clk[0],
|
||||
&dss_clk[1],
|
||||
&dss_54m_clk,
|
||||
&dss_l3_iclk,
|
||||
&dss_l4_iclk,
|
||||
&omapctrl_clk,
|
||||
|
||||
NULL
|
||||
};
|
||||
|
||||
@ -1230,12 +713,6 @@ void omap_clk_init(struct omap_mpu_state_s *mpu)
|
||||
flag = CLOCK_IN_OMAP310;
|
||||
else if (cpu_is_omap1510(mpu))
|
||||
flag = CLOCK_IN_OMAP1510;
|
||||
else if (cpu_is_omap2410(mpu) || cpu_is_omap2420(mpu))
|
||||
flag = CLOCK_IN_OMAP242X;
|
||||
else if (cpu_is_omap2430(mpu))
|
||||
flag = CLOCK_IN_OMAP243X;
|
||||
else if (cpu_is_omap3430(mpu))
|
||||
flag = CLOCK_IN_OMAP243X;
|
||||
else
|
||||
return;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user