mirror of https://gitlab.com/qemu-project/qemu
target-ppc: optimize mullw and make the code more readable
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5657 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -1234,20 +1234,9 @@ GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
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/* mullw mullw. */
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/* mullw mullw. */
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GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
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GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
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{
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{
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#if defined(TARGET_PPC64)
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TCGv t0, t1;
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t0 = tcg_temp_new(TCG_TYPE_TL);
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t1 = tcg_temp_new(TCG_TYPE_TL);
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tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
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tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
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tcg_gen_mul_tl(t0, t0, t1);
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tcg_temp_free(t0);
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tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], t0);
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tcg_temp_free(t1);
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#else
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tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
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tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
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cpu_gpr[rB(ctx->opcode)]);
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cpu_gpr[rB(ctx->opcode)]);
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#endif
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tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
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if (unlikely(Rc(ctx->opcode) != 0))
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if (unlikely(Rc(ctx->opcode) != 0))
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gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
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gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
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}
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}
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