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bugfix: Use gicr_typer in arm_gicv3_icc_reset

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The KVM_VGIC_ATTR macro expect the second parameter as gicr_typer,
of which high 32bit is constructed by mp_affinity. For most case,
the high 32bit of mp_affinity is zero, so it will always access the
ICC_CTLR_EL1 of CPU0.

Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
Message-id: 20200413091552.62748-2-zhukeqian1@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Keqian Zhu 2020-04-13 17:15:50 +08:00 committed by Peter Maydell
parent c8aeef3aed
commit 1e11a139bf
1 changed files with 1 additions and 3 deletions
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4
hw/intc/arm_gicv3_kvm.c
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@ -658,13 +658,11 @@ static void kvm_arm_gicv3_get(GICv3State *s)
static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{ {
ARMCPU *cpu;
GICv3State *s; GICv3State *s;
GICv3CPUState *c; GICv3CPUState *c;
c = (GICv3CPUState *)env->gicv3state; c = (GICv3CPUState *)env->gicv3state;
s = c->gic; s = c->gic;
cpu = ARM_CPU(c->cpu);
c->icc_pmr_el1 = 0; c->icc_pmr_el1 = 0;
c->icc_bpr[GICV3_G0] = GIC_MIN_BPR; c->icc_bpr[GICV3_G0] = GIC_MIN_BPR;
@ -681,7 +679,7 @@ static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
/* Initialize to actual HW supported configuration */ /* Initialize to actual HW supported configuration */
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
KVM_VGIC_ATTR(ICC_CTLR_EL1, cpu->mp_affinity), KVM_VGIC_ATTR(ICC_CTLR_EL1, c->gicr_typer),
&c->icc_ctlr_el1[GICV3_NS], false, &error_abort); &c->icc_ctlr_el1[GICV3_NS], false, &error_abort);
c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS]; c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS];