tcg/arm: Introduce HostAddress
Collect the parts of the host address, and condition, into a struct. Merge tcg_out_qemu_*_{index,direct} and use it. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
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737fb471ed
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@ -1337,6 +1337,13 @@ static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
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tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf);
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}
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typedef struct {
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ARMCond cond;
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TCGReg base;
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int index;
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bool index_scratch;
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} HostAddress;
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#ifdef CONFIG_SOFTMMU
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/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
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* int mmu_idx, uintptr_t ra)
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@ -1696,29 +1703,49 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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}
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#endif /* SOFTMMU */
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static void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc,
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TCGReg datalo, TCGReg datahi,
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TCGReg addrlo, TCGReg addend,
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bool scratch_addend)
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static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo,
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TCGReg datahi, HostAddress h)
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{
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TCGReg base;
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/* Byte swapping is left to middle-end expansion. */
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tcg_debug_assert((opc & MO_BSWAP) == 0);
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switch (opc & MO_SSIZE) {
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case MO_UB:
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tcg_out_ld8_r(s, COND_AL, datalo, addrlo, addend);
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if (h.index < 0) {
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tcg_out_ld8_12(s, h.cond, datalo, h.base, 0);
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} else {
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tcg_out_ld8_r(s, h.cond, datalo, h.base, h.index);
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}
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break;
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case MO_SB:
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tcg_out_ld8s_r(s, COND_AL, datalo, addrlo, addend);
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if (h.index < 0) {
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tcg_out_ld8s_8(s, h.cond, datalo, h.base, 0);
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} else {
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tcg_out_ld8s_r(s, h.cond, datalo, h.base, h.index);
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}
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break;
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case MO_UW:
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tcg_out_ld16u_r(s, COND_AL, datalo, addrlo, addend);
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if (h.index < 0) {
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tcg_out_ld16u_8(s, h.cond, datalo, h.base, 0);
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} else {
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tcg_out_ld16u_r(s, h.cond, datalo, h.base, h.index);
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}
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break;
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case MO_SW:
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tcg_out_ld16s_r(s, COND_AL, datalo, addrlo, addend);
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if (h.index < 0) {
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tcg_out_ld16s_8(s, h.cond, datalo, h.base, 0);
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} else {
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tcg_out_ld16s_r(s, h.cond, datalo, h.base, h.index);
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}
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break;
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case MO_UL:
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tcg_out_ld32_r(s, COND_AL, datalo, addrlo, addend);
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if (h.index < 0) {
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tcg_out_ld32_12(s, h.cond, datalo, h.base, 0);
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} else {
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tcg_out_ld32_r(s, h.cond, datalo, h.base, h.index);
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}
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break;
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case MO_UQ:
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/* We used pair allocation for datalo, so already should be aligned. */
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@ -1726,87 +1753,59 @@ static void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc,
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tcg_debug_assert(datahi == datalo + 1);
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/* LDRD requires alignment; double-check that. */
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if (get_alignment_bits(opc) >= MO_64) {
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if (h.index < 0) {
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tcg_out_ldrd_8(s, h.cond, datalo, h.base, 0);
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break;
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}
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/*
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* Rm (the second address op) must not overlap Rt or Rt + 1.
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* Since datalo is aligned, we can simplify the test via alignment.
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* Flip the two address arguments if that works.
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*/
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if ((addend & ~1) != datalo) {
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tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend);
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if ((h.index & ~1) != datalo) {
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tcg_out_ldrd_r(s, h.cond, datalo, h.base, h.index);
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break;
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}
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if ((addrlo & ~1) != datalo) {
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tcg_out_ldrd_r(s, COND_AL, datalo, addend, addrlo);
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if ((h.base & ~1) != datalo) {
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tcg_out_ldrd_r(s, h.cond, datalo, h.index, h.base);
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break;
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}
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}
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if (scratch_addend) {
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tcg_out_ld32_rwb(s, COND_AL, datalo, addend, addrlo);
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tcg_out_ld32_12(s, COND_AL, datahi, addend, 4);
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if (h.index < 0) {
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base = h.base;
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if (datalo == h.base) {
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tcg_out_mov_reg(s, h.cond, TCG_REG_TMP, base);
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base = TCG_REG_TMP;
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}
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} else if (h.index_scratch) {
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tcg_out_ld32_rwb(s, h.cond, datalo, h.index, h.base);
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tcg_out_ld32_12(s, h.cond, datahi, h.index, 4);
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break;
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} else {
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tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_TMP,
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addend, addrlo, SHIFT_IMM_LSL(0));
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tcg_out_ld32_12(s, COND_AL, datalo, TCG_REG_TMP, 0);
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tcg_out_ld32_12(s, COND_AL, datahi, TCG_REG_TMP, 4);
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tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP,
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h.base, h.index, SHIFT_IMM_LSL(0));
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base = TCG_REG_TMP;
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}
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tcg_out_ld32_12(s, h.cond, datalo, base, 0);
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tcg_out_ld32_12(s, h.cond, datahi, base, 4);
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break;
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default:
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g_assert_not_reached();
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}
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}
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#ifndef CONFIG_SOFTMMU
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static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo,
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TCGReg datahi, TCGReg addrlo)
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{
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/* Byte swapping is left to middle-end expansion. */
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tcg_debug_assert((opc & MO_BSWAP) == 0);
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switch (opc & MO_SSIZE) {
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case MO_UB:
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tcg_out_ld8_12(s, COND_AL, datalo, addrlo, 0);
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break;
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case MO_SB:
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tcg_out_ld8s_8(s, COND_AL, datalo, addrlo, 0);
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break;
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case MO_UW:
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tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0);
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break;
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case MO_SW:
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tcg_out_ld16s_8(s, COND_AL, datalo, addrlo, 0);
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break;
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case MO_UL:
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tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0);
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break;
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case MO_UQ:
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/* We used pair allocation for datalo, so already should be aligned. */
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tcg_debug_assert((datalo & 1) == 0);
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tcg_debug_assert(datahi == datalo + 1);
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/* LDRD requires alignment; double-check that. */
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if (get_alignment_bits(opc) >= MO_64) {
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tcg_out_ldrd_8(s, COND_AL, datalo, addrlo, 0);
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} else if (datalo == addrlo) {
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tcg_out_ld32_12(s, COND_AL, datahi, addrlo, 4);
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tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0);
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} else {
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tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0);
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tcg_out_ld32_12(s, COND_AL, datahi, addrlo, 4);
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}
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break;
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default:
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g_assert_not_reached();
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}
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}
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#endif
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static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
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TCGReg addrlo, TCGReg addrhi,
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MemOpIdx oi, TCGType data_type)
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{
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MemOp opc = get_memop(oi);
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HostAddress h;
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#ifdef CONFIG_SOFTMMU
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TCGReg addend= tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(oi), 1);
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h.cond = COND_AL;
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h.base = addrlo;
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h.index_scratch = true;
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h.index = tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(oi), 1);
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/*
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* This a conditional BL only to load a pointer within this opcode into
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@ -1815,80 +1814,51 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
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tcg_insn_unit *label_ptr = s->code_ptr;
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tcg_out_bl_imm(s, COND_NE, 0);
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tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend, true);
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tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h);
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add_qemu_ldst_label(s, true, oi, data_type, datalo, datahi,
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addrlo, addrhi, s->code_ptr, label_ptr);
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#else /* !CONFIG_SOFTMMU */
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#else
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unsigned a_bits = get_alignment_bits(opc);
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if (a_bits) {
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tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
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}
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if (guest_base) {
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tcg_out_qemu_ld_index(s, opc, datalo, datahi,
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addrlo, TCG_REG_GUEST_BASE, false);
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} else {
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tcg_out_qemu_ld_direct(s, opc, datalo, datahi, addrlo);
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}
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h.cond = COND_AL;
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h.base = addrlo;
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h.index = guest_base ? TCG_REG_GUEST_BASE : -1;
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h.index_scratch = false;
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tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h);
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#endif
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}
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static void tcg_out_qemu_st_index(TCGContext *s, ARMCond cond, MemOp opc,
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TCGReg datalo, TCGReg datahi,
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TCGReg addrlo, TCGReg addend,
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bool scratch_addend)
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{
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/* Byte swapping is left to middle-end expansion. */
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tcg_debug_assert((opc & MO_BSWAP) == 0);
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switch (opc & MO_SIZE) {
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case MO_8:
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tcg_out_st8_r(s, cond, datalo, addrlo, addend);
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break;
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case MO_16:
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tcg_out_st16_r(s, cond, datalo, addrlo, addend);
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break;
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case MO_32:
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tcg_out_st32_r(s, cond, datalo, addrlo, addend);
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break;
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case MO_64:
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/* We used pair allocation for datalo, so already should be aligned. */
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tcg_debug_assert((datalo & 1) == 0);
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tcg_debug_assert(datahi == datalo + 1);
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/* STRD requires alignment; double-check that. */
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if (get_alignment_bits(opc) >= MO_64) {
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tcg_out_strd_r(s, cond, datalo, addrlo, addend);
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} else if (scratch_addend) {
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tcg_out_st32_rwb(s, cond, datalo, addend, addrlo);
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tcg_out_st32_12(s, cond, datahi, addend, 4);
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} else {
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tcg_out_dat_reg(s, cond, ARITH_ADD, TCG_REG_TMP,
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addend, addrlo, SHIFT_IMM_LSL(0));
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tcg_out_st32_12(s, cond, datalo, TCG_REG_TMP, 0);
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tcg_out_st32_12(s, cond, datahi, TCG_REG_TMP, 4);
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}
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break;
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default:
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g_assert_not_reached();
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}
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}
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#ifndef CONFIG_SOFTMMU
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static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo,
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TCGReg datahi, TCGReg addrlo)
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TCGReg datahi, HostAddress h)
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{
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/* Byte swapping is left to middle-end expansion. */
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tcg_debug_assert((opc & MO_BSWAP) == 0);
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switch (opc & MO_SIZE) {
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case MO_8:
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tcg_out_st8_12(s, COND_AL, datalo, addrlo, 0);
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if (h.index < 0) {
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tcg_out_st8_12(s, h.cond, datalo, h.base, 0);
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} else {
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tcg_out_st8_r(s, h.cond, datalo, h.base, h.index);
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}
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break;
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case MO_16:
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tcg_out_st16_8(s, COND_AL, datalo, addrlo, 0);
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if (h.index < 0) {
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tcg_out_st16_8(s, h.cond, datalo, h.base, 0);
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} else {
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tcg_out_st16_r(s, h.cond, datalo, h.base, h.index);
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}
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break;
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case MO_32:
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tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0);
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if (h.index < 0) {
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tcg_out_st32_12(s, h.cond, datalo, h.base, 0);
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} else {
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tcg_out_st32_r(s, h.cond, datalo, h.base, h.index);
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}
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break;
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case MO_64:
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/* We used pair allocation for datalo, so already should be aligned. */
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@ -1896,29 +1866,39 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo,
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tcg_debug_assert(datahi == datalo + 1);
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/* STRD requires alignment; double-check that. */
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if (get_alignment_bits(opc) >= MO_64) {
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tcg_out_strd_8(s, COND_AL, datalo, addrlo, 0);
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if (h.index < 0) {
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tcg_out_strd_8(s, h.cond, datalo, h.base, 0);
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} else {
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tcg_out_strd_r(s, h.cond, datalo, h.base, h.index);
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}
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} else if (h.index_scratch) {
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tcg_out_st32_rwb(s, h.cond, datalo, h.index, h.base);
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tcg_out_st32_12(s, h.cond, datahi, h.index, 4);
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} else {
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tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0);
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tcg_out_st32_12(s, COND_AL, datahi, addrlo, 4);
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tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP,
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h.base, h.index, SHIFT_IMM_LSL(0));
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tcg_out_st32_12(s, h.cond, datalo, TCG_REG_TMP, 0);
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tcg_out_st32_12(s, h.cond, datahi, TCG_REG_TMP, 4);
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}
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break;
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default:
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g_assert_not_reached();
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}
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}
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#endif
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static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
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TCGReg addrlo, TCGReg addrhi,
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MemOpIdx oi, TCGType data_type)
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{
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MemOp opc = get_memop(oi);
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HostAddress h;
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#ifdef CONFIG_SOFTMMU
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TCGReg addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(oi), 0);
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tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi,
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addrlo, addend, true);
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h.cond = COND_EQ;
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h.base = addrlo;
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h.index_scratch = true;
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h.index = tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(oi), 0);
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tcg_out_qemu_st_direct(s, opc, datalo, datahi, h);
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/* The conditional call must come last, as we're going to return here. */
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tcg_insn_unit *label_ptr = s->code_ptr;
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@ -1926,17 +1906,19 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
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add_qemu_ldst_label(s, false, oi, data_type, datalo, datahi,
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addrlo, addrhi, s->code_ptr, label_ptr);
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#else /* !CONFIG_SOFTMMU */
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#else
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unsigned a_bits = get_alignment_bits(opc);
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h.cond = COND_AL;
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if (a_bits) {
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tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits);
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h.cond = COND_EQ;
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}
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if (guest_base) {
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tcg_out_qemu_st_index(s, COND_AL, opc, datalo, datahi,
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addrlo, TCG_REG_GUEST_BASE, false);
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} else {
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tcg_out_qemu_st_direct(s, opc, datalo, datahi, addrlo);
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}
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h.base = addrlo;
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h.index = guest_base ? TCG_REG_GUEST_BASE : -1;
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h.index_scratch = false;
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tcg_out_qemu_st_direct(s, opc, datalo, datahi, h);
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#endif
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}
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