target-arm: emulate aarch64's LL/SC using cmpxchg helpers
Emulating LL/SC with cmpxchg is not correct, since it can suffer from the ABA problem. Portable parallel code, however, is written assuming only cmpxchg--and not LL/SC--is available. This means that in practice emulating LL/SC with cmpxchg is a viable alternative. The appended emulates LL/SC pairs in aarch64 with cmpxchg helpers. This works in both user and system mode. In usermode, it avoids pausing all other CPUs to perform the LL/SC pair. The subsequent performance and scalability improvement is significant, as the plots below show. They plot the throughput of atomic_add-bench compiled for ARM and executed on a 64-core x86 machine. Hi-res plots: http://imgur.com/a/JVc8Y atomic_add-bench: 1000000 ops/thread, [0,1] range 18 ++---------+----------+---------+----------+----------+----------+---++ +cmpxchg +-E--+ + + + + + | 16 ++master +-H--+ ++ || | 14 ++ ++ | | | 12 ++| ++ | | | 10 ++++ ++ 8 ++E ++ |+++ | 6 ++ | ++ | | | 4 ++ | ++ | | | 2 +H++E+--- ++ + | +E++----+E+---+--+E+----++E+------+E+------+E++----+E+---+--+E| 0 ++H-H----H-+-----H----+---------+----------+----------+----------+---++ 0 10 20 30 40 50 60 Number of threads atomic_add-bench: 1000000 ops/thread, [0,2] range 18 ++---------+----------+---------+----------+----------+----------+---++ +cmpxchg +-E--+ + + + + + | 16 ++master +-H--+ ++ | | | 14 ++E ++ | | | 12 ++| ++ |+++ | 10 ++ | ++ 8 ++ | ++ | | | 6 ++ | ++ | | | 4 ++ | ++ | +E+--- | 2 +H+ +E+-----+++ +++ +++ ---+E+-----+E+------+++ +++ + +E+---+--+E+----++E+------+E+--- ++++ +++ + +E| 0 ++H-H----H-+-----H----+---------+----------+----------+----------+---++ 0 10 20 30 40 50 60 Number of threads atomic_add-bench: 1000000 ops/thread, [0,128] range 70 ++---------+----------+---------+----------+----------+----------+---++ +cmpxchg +-E--+ + + + + + | 60 ++master +-H--+ +++ ---+E+-----+E+------+E+ | +E+------E-------+E+--- | | --- +++ | 50 ++ +++--- ++ | -+E+ | 40 ++ +++---- ++ | E- | | --| | 30 ++ -- +++ ++ | +E+ | 20 ++E+ ++ |E+ | | | 10 ++ ++ + + + + + + + | 0 +HH-H----H-+-----H----+---------+----------+----------+----------+---++ 0 10 20 30 40 50 60 Number of threads atomic_add-bench: 1000000 ops/thread, [0,1024] range 160 ++---------+---------+----------+---------+----------+----------+---++ +cmpxchg +-E--+ + + + + + | 140 ++master +-H--+ +++ +++ | -+E+-----+E+-------E| 120 ++ +++ ---- +++ | +++ ----E-- | 100 ++ --E--- +++ ++ | +++ ---- +++ | 80 ++ --E-- ++ | ---- +++ | | -+E+ | 60 ++ ---- +++ ++ | +E+- | 40 ++ -- ++ | +E+ | 20 +EE+ ++ +++ + + + + + + | 0 +HH-H---H--+-----H---+----------+---------+----------+----------+---++ 0 10 20 30 40 50 60 Number of threads [rth: Rearrange 128-bit cmpxchg helper. Enforce alignment on LL.] Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <1467054136-10430-28-git-send-email-cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Emilio G. Cota
Richard Henderson
parent
cf12bce088
commit
1dd089d0ee
@ -27,6 +27,10 @@
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#include "qemu/bitops.h"
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#include "internals.h"
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#include "qemu/crc32c.h"
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#include "exec/exec-all.h"
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#include "exec/cpu_ldst.h"
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#include "qemu/int128.h"
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#include "tcg.h"
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#include <zlib.h> /* For crc32 */
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/* C2.4.7 Multiply and divide */
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@ -444,3 +448,112 @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, uint32_t bytes)
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/* Linux crc32c converts the output to one's complement. */
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return crc32c(acc, buf, bytes) ^ 0xffffffff;
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}
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/* Returns 0 on success; 1 otherwise. */
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uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr,
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uint64_t new_lo, uint64_t new_hi)
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{
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uintptr_t ra = GETPC();
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Int128 oldv, cmpv, newv;
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bool success;
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cmpv = int128_make128(env->exclusive_val, env->exclusive_high);
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newv = int128_make128(new_lo, new_hi);
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if (parallel_cpus) {
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#ifndef CONFIG_ATOMIC128
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cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
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#else
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int mem_idx = cpu_mmu_index(env, false);
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TCGMemOpIdx oi = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
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oldv = helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra);
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success = int128_eq(oldv, cmpv);
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#endif
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} else {
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uint64_t o0, o1;
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#ifdef CONFIG_USER_ONLY
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/* ??? Enforce alignment. */
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uint64_t *haddr = g2h(addr);
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o0 = ldq_le_p(haddr + 0);
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o1 = ldq_le_p(haddr + 1);
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oldv = int128_make128(o0, o1);
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success = int128_eq(oldv, cmpv);
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if (success) {
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stq_le_p(haddr + 0, int128_getlo(newv));
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stq_le_p(haddr + 1, int128_gethi(newv));
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}
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#else
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int mem_idx = cpu_mmu_index(env, false);
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TCGMemOpIdx oi0 = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
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TCGMemOpIdx oi1 = make_memop_idx(MO_LEQ, mem_idx);
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o0 = helper_le_ldq_mmu(env, addr + 0, oi0, ra);
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o1 = helper_le_ldq_mmu(env, addr + 8, oi1, ra);
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oldv = int128_make128(o0, o1);
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success = int128_eq(oldv, cmpv);
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if (success) {
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helper_le_stq_mmu(env, addr + 0, int128_getlo(newv), oi1, ra);
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helper_le_stq_mmu(env, addr + 8, int128_gethi(newv), oi1, ra);
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}
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#endif
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}
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return !success;
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}
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uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr,
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uint64_t new_lo, uint64_t new_hi)
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{
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uintptr_t ra = GETPC();
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Int128 oldv, cmpv, newv;
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bool success;
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cmpv = int128_make128(env->exclusive_val, env->exclusive_high);
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newv = int128_make128(new_lo, new_hi);
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if (parallel_cpus) {
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#ifndef CONFIG_ATOMIC128
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cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
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#else
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int mem_idx = cpu_mmu_index(env, false);
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TCGMemOpIdx oi = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx);
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oldv = helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra);
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success = int128_eq(oldv, cmpv);
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#endif
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} else {
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uint64_t o0, o1;
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#ifdef CONFIG_USER_ONLY
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/* ??? Enforce alignment. */
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uint64_t *haddr = g2h(addr);
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o1 = ldq_be_p(haddr + 0);
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o0 = ldq_be_p(haddr + 1);
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oldv = int128_make128(o0, o1);
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success = int128_eq(oldv, cmpv);
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if (success) {
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stq_be_p(haddr + 0, int128_gethi(newv));
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stq_be_p(haddr + 1, int128_getlo(newv));
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}
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#else
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int mem_idx = cpu_mmu_index(env, false);
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TCGMemOpIdx oi0 = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx);
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TCGMemOpIdx oi1 = make_memop_idx(MO_BEQ, mem_idx);
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o1 = helper_be_ldq_mmu(env, addr + 0, oi0, ra);
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o0 = helper_be_ldq_mmu(env, addr + 8, oi1, ra);
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oldv = int128_make128(o0, o1);
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success = int128_eq(oldv, cmpv);
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if (success) {
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helper_be_stq_mmu(env, addr + 0, int128_gethi(newv), oi1, ra);
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helper_be_stq_mmu(env, addr + 8, int128_getlo(newv), oi1, ra);
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}
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#endif
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}
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return !success;
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}
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@ -46,3 +46,5 @@ DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
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DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env)
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DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
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DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
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DEF_HELPER_FLAGS_4(paired_cmpxchg64_le, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
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DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
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@ -1839,37 +1839,41 @@ static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
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}
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}
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/*
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* Load/Store exclusive instructions are implemented by remembering
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* the value/address loaded, and seeing if these are the same
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* when the store is performed. This is not actually the architecturally
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* mandated semantics, but it works for typical guest code sequences
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* and avoids having to monitor regular stores.
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*
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* In system emulation mode only one CPU will be running at once, so
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* this sequence is effectively atomic. In user emulation mode we
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* throw an exception and handle the atomic operation elsewhere.
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*/
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static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
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TCGv_i64 addr, int size, bool is_pair)
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{
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TCGv_i64 tmp = tcg_temp_new_i64();
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TCGMemOp memop = s->be_data + size;
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TCGMemOp be = s->be_data;
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g_assert(size <= 3);
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tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), memop);
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if (is_pair) {
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TCGv_i64 addr2 = tcg_temp_new_i64();
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TCGv_i64 hitmp = tcg_temp_new_i64();
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g_assert(size >= 2);
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tcg_gen_addi_i64(addr2, addr, 1 << size);
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tcg_gen_qemu_ld_i64(hitmp, addr2, get_mem_index(s), memop);
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if (size == 3) {
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TCGv_i64 addr2 = tcg_temp_new_i64();
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tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s),
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MO_64 | MO_ALIGN_16 | be);
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tcg_gen_addi_i64(addr2, addr, 8);
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tcg_gen_qemu_ld_i64(hitmp, addr2, get_mem_index(s),
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MO_64 | MO_ALIGN | be);
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tcg_temp_free_i64(addr2);
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} else {
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g_assert(size == 2);
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tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s),
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MO_64 | MO_ALIGN | be);
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if (be == MO_LE) {
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tcg_gen_extr32_i64(tmp, hitmp, tmp);
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} else {
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tcg_gen_extr32_i64(hitmp, tmp, tmp);
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}
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}
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tcg_gen_mov_i64(cpu_exclusive_high, hitmp);
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tcg_gen_mov_i64(cpu_reg(s, rt2), hitmp);
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tcg_temp_free_i64(hitmp);
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} else {
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tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), size | MO_ALIGN | be);
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}
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tcg_gen_mov_i64(cpu_exclusive_val, tmp);
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@ -1879,16 +1883,6 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
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tcg_gen_mov_i64(cpu_exclusive_addr, addr);
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}
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#ifdef CONFIG_USER_ONLY
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static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
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TCGv_i64 addr, int size, int is_pair)
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{
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tcg_gen_mov_i64(cpu_exclusive_test, addr);
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tcg_gen_movi_i32(cpu_exclusive_info,
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size | is_pair << 2 | (rd << 4) | (rt << 9) | (rt2 << 14));
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gen_exception_internal_insn(s, 4, EXCP_STREX);
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}
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#else
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static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
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TCGv_i64 inaddr, int size, int is_pair)
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{
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@ -1916,46 +1910,42 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
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tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);
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tmp = tcg_temp_new_i64();
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tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), s->be_data + size);
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tcg_gen_brcond_i64(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label);
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tcg_temp_free_i64(tmp);
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if (is_pair) {
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TCGv_i64 addrhi = tcg_temp_new_i64();
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TCGv_i64 tmphi = tcg_temp_new_i64();
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tcg_gen_addi_i64(addrhi, addr, 1 << size);
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tcg_gen_qemu_ld_i64(tmphi, addrhi, get_mem_index(s),
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s->be_data + size);
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tcg_gen_brcond_i64(TCG_COND_NE, tmphi, cpu_exclusive_high, fail_label);
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tcg_temp_free_i64(tmphi);
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tcg_temp_free_i64(addrhi);
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if (size == 2) {
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TCGv_i64 val = tcg_temp_new_i64();
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tcg_gen_concat32_i64(tmp, cpu_reg(s, rt), cpu_reg(s, rt2));
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tcg_gen_concat32_i64(val, cpu_exclusive_val, cpu_exclusive_high);
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tcg_gen_atomic_cmpxchg_i64(tmp, addr, val, tmp,
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get_mem_index(s),
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size | MO_ALIGN | s->be_data);
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tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, val);
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tcg_temp_free_i64(val);
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} else if (s->be_data == MO_LE) {
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gen_helper_paired_cmpxchg64_le(tmp, cpu_env, addr, cpu_reg(s, rt),
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cpu_reg(s, rt2));
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} else {
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gen_helper_paired_cmpxchg64_be(tmp, cpu_env, addr, cpu_reg(s, rt),
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cpu_reg(s, rt2));
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}
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/* We seem to still have the exclusive monitor, so do the store */
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tcg_gen_qemu_st_i64(cpu_reg(s, rt), addr, get_mem_index(s),
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s->be_data + size);
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if (is_pair) {
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TCGv_i64 addrhi = tcg_temp_new_i64();
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tcg_gen_addi_i64(addrhi, addr, 1 << size);
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tcg_gen_qemu_st_i64(cpu_reg(s, rt2), addrhi,
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get_mem_index(s), s->be_data + size);
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tcg_temp_free_i64(addrhi);
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} else {
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TCGv_i64 val = cpu_reg(s, rt);
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tcg_gen_atomic_cmpxchg_i64(tmp, addr, cpu_exclusive_val, val,
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get_mem_index(s),
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size | MO_ALIGN | s->be_data);
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tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val);
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}
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tcg_temp_free_i64(addr);
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tcg_gen_movi_i64(cpu_reg(s, rd), 0);
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tcg_gen_mov_i64(cpu_reg(s, rd), tmp);
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tcg_temp_free_i64(tmp);
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tcg_gen_br(done_label);
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gen_set_label(fail_label);
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tcg_gen_movi_i64(cpu_reg(s, rd), 1);
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gen_set_label(done_label);
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tcg_gen_movi_i64(cpu_exclusive_addr, -1);
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}
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#endif
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/* Update the Sixty-Four bit (SF) registersize. This logic is derived
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* from the ARMv8 specs for LDR (Shared decode for all encodings).
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