microblaze: avoid "naked" qemu_log
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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79e8ed3597
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1d512a65ac
@ -128,7 +128,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
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switch (cs->exception_index) {
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case EXCP_HW_EXCP:
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if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) {
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qemu_log("Exception raised on system without exceptions!\n");
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qemu_log_mask(LOG_GUEST_ERROR, "Exception raised on system without exceptions!\n");
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return;
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}
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@ -60,7 +60,7 @@ static void mmu_change_pid(CPUMBState *env, unsigned int newpid)
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uint32_t t;
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if (newpid & ~0xff)
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qemu_log("Illegal rpid=%x\n", newpid);
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qemu_log_mask(LOG_GUEST_ERROR, "Illegal rpid=%x\n", newpid);
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for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {
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/* Lookup and decode. */
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@ -121,7 +121,7 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu,
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t0 &= 0x3;
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if (tlb_zsel > mmu->c_mmu_zones) {
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qemu_log("tlb zone select out of range! %d\n", tlb_zsel);
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qemu_log_mask(LOG_GUEST_ERROR, "tlb zone select out of range! %d\n", tlb_zsel);
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t0 = 1; /* Ignore. */
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}
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@ -183,7 +183,7 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn)
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uint32_t r;
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if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
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qemu_log("MMU access on MMU-less system\n");
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qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");
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return 0;
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}
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@ -192,7 +192,7 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn)
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case MMU_R_TLBLO:
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case MMU_R_TLBHI:
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if (!(env->mmu.c_mmu_tlb_access & 1)) {
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qemu_log("Invalid access to MMU reg %d\n", rn);
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qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
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return 0;
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}
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@ -204,7 +204,7 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn)
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case MMU_R_PID:
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case MMU_R_ZPR:
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if (!(env->mmu.c_mmu_tlb_access & 1)) {
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qemu_log("Invalid access to MMU reg %d\n", rn);
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qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
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return 0;
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}
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r = env->mmu.regs[rn];
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@ -224,7 +224,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
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D(qemu_log("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn]));
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if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
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qemu_log("MMU access on MMU-less system\n");
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qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");
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return;
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}
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@ -235,7 +235,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
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i = env->mmu.regs[MMU_R_TLBX] & 0xff;
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if (rn == MMU_R_TLBHI) {
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if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0))
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qemu_log("invalidating index %x at pc=%x\n",
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qemu_log_mask(LOG_GUEST_ERROR, "invalidating index %x at pc=%x\n",
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i, env->sregs[SR_PC]);
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env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff;
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mmu_flush_idx(env, i);
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@ -246,7 +246,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
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break;
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case MMU_R_ZPR:
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if (env->mmu.c_mmu_tlb_access <= 1) {
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qemu_log("Invalid access to MMU reg %d\n", rn);
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qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
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return;
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}
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@ -259,7 +259,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
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break;
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case MMU_R_PID:
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if (env->mmu.c_mmu_tlb_access <= 1) {
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qemu_log("Invalid access to MMU reg %d\n", rn);
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qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
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return;
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}
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@ -274,7 +274,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
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int hit;
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if (env->mmu.c_mmu_tlb_access <= 1) {
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qemu_log("Invalid access to MMU reg %d\n", rn);
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qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
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return;
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}
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@ -55,7 +55,7 @@ void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
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int nonblock = ctrl & STREAM_NONBLOCK;
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int exception = ctrl & STREAM_EXCEPTION;
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qemu_log("Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
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qemu_log_mask(LOG_UNIMP, "Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
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id, data,
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test ? "t" : "",
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nonblock ? "n" : "",
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@ -72,7 +72,7 @@ uint32_t helper_get(uint32_t id, uint32_t ctrl)
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int nonblock = ctrl & STREAM_NONBLOCK;
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int exception = ctrl & STREAM_EXCEPTION;
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qemu_log("Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
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qemu_log_mask(LOG_UNIMP, "Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
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id,
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test ? "t" : "",
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nonblock ? "n" : "",
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@ -465,8 +465,8 @@ void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
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void helper_stackprot(CPUMBState *env, uint32_t addr)
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{
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if (addr < env->slr || addr > env->shr) {
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qemu_log("Stack protector violation at %x %x %x\n",
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addr, env->slr, env->shr);
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qemu_log_mask(CPU_LOG_INT, "Stack protector violation at %x %x %x\n",
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addr, env->slr, env->shr);
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env->sregs[SR_EAR] = addr;
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env->sregs[SR_ESR] = ESR_EC_STACKPROT;
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helper_raise_exception(env, EXCP_HW_EXCP);
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@ -1516,7 +1516,7 @@ static void dec_null(DisasContext *dc)
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t_gen_raise_exception(dc, EXCP_HW_EXCP);
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return;
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}
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qemu_log ("unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode);
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qemu_log_mask(LOG_GUEST_ERROR, "unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode);
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dc->abort_at_next_insn = 1;
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}
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