hw/gpio: Implement STM32L4x5 GPIO
Features supported :
- the 8 STM32L4x5 GPIOs are initialized with their reset values
(except IDR, see below)
- input mode : setting a pin in input mode "externally" (using input
irqs) results in an out irq (transmitted to SYSCFG)
- output mode : setting a bit in ODR sets the corresponding out irq
(if this line is configured in output mode)
- pull-up, pull-down
- push-pull, open-drain
Difference with the real GPIOs :
- Alternate Function and Analog mode aren't implemented :
pins in AF/Analog behave like pins in input mode
- floating pins stay at their last value
- register IDR reset values differ from the real one :
values are coherent with the other registers reset values
and the fact that AF/Analog modes aren't implemented
- setting I/O output speed isn't supported
- locking port bits isn't supported
- ADC function isn't supported
- GPIOH has 16 pins instead of 2 pins
- writing to registers LCKR, AFRL, AFRH and ASCR is ineffective
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20240305210444.310665-2-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Inès Varhol
Peter Maydell
parent
c10a9a517a
commit
1cdcfb6e93
@ -1133,6 +1133,7 @@ F: hw/arm/stm32l4x5_soc.c
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F: hw/misc/stm32l4x5_exti.c
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F: hw/misc/stm32l4x5_syscfg.c
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F: hw/misc/stm32l4x5_rcc.c
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F: hw/gpio/stm32l4x5_gpio.c
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F: include/hw/*/stm32l4x5_*.h
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B-L475E-IOT01A IoT Node
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@ -18,6 +18,7 @@ Currently B-L475E-IOT01A machine's only supports the following devices:
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- STM32L4x5 EXTI (Extended interrupts and events controller)
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- STM32L4x5 SYSCFG (System configuration controller)
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- STM32L4x5 RCC (Reset and clock control)
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- STM32L4x5 GPIOs (General-purpose I/Os)
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Missing devices
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"""""""""""""""
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@ -25,7 +26,6 @@ Missing devices
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The B-L475E-IOT01A does *not* support the following devices:
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- Serial ports (UART)
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- General-purpose I/Os (GPIO)
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- Analog to Digital Converter (ADC)
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- SPI controller
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- Timer controller (TIMER)
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@ -16,3 +16,6 @@ config GPIO_PWR
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config SIFIVE_GPIO
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bool
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config STM32L4X5_GPIO
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bool
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@ -13,5 +13,6 @@ system_ss.add(when: 'CONFIG_RASPI', if_true: files(
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'bcm2835_gpio.c',
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'bcm2838_gpio.c'
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))
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system_ss.add(when: 'CONFIG_STM32L4X5_SOC', if_true: files('stm32l4x5_gpio.c'))
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system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
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system_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))
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477
hw/gpio/stm32l4x5_gpio.c
Normal file
477
hw/gpio/stm32l4x5_gpio.c
Normal file
@ -0,0 +1,477 @@
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/*
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* STM32L4x5 GPIO (General Purpose Input/Ouput)
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*
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* Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
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* Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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/*
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* The reference used is the STMicroElectronics RM0351 Reference manual
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* for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
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* https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "hw/gpio/stm32l4x5_gpio.h"
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#include "hw/irq.h"
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#include "hw/qdev-clock.h"
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#include "hw/qdev-properties.h"
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#include "qapi/visitor.h"
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#include "qapi/error.h"
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#include "migration/vmstate.h"
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#include "trace.h"
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#define GPIO_MODER 0x00
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#define GPIO_OTYPER 0x04
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#define GPIO_OSPEEDR 0x08
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#define GPIO_PUPDR 0x0C
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#define GPIO_IDR 0x10
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#define GPIO_ODR 0x14
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#define GPIO_BSRR 0x18
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#define GPIO_LCKR 0x1C
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#define GPIO_AFRL 0x20
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#define GPIO_AFRH 0x24
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#define GPIO_BRR 0x28
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#define GPIO_ASCR 0x2C
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/* 0b11111111_11111111_00000000_00000000 */
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#define RESERVED_BITS_MASK 0xFFFF0000
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static void update_gpio_idr(Stm32l4x5GpioState *s);
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static bool is_pull_up(Stm32l4x5GpioState *s, unsigned pin)
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{
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return extract32(s->pupdr, 2 * pin, 2) == 1;
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}
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static bool is_pull_down(Stm32l4x5GpioState *s, unsigned pin)
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{
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return extract32(s->pupdr, 2 * pin, 2) == 2;
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}
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static bool is_output(Stm32l4x5GpioState *s, unsigned pin)
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{
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return extract32(s->moder, 2 * pin, 2) == 1;
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}
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static bool is_open_drain(Stm32l4x5GpioState *s, unsigned pin)
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{
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return extract32(s->otyper, pin, 1) == 1;
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}
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static bool is_push_pull(Stm32l4x5GpioState *s, unsigned pin)
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{
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return extract32(s->otyper, pin, 1) == 0;
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}
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static void stm32l4x5_gpio_reset_hold(Object *obj)
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{
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Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
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s->moder = s->moder_reset;
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s->otyper = 0x00000000;
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s->ospeedr = s->ospeedr_reset;
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s->pupdr = s->pupdr_reset;
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s->idr = 0x00000000;
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s->odr = 0x00000000;
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s->lckr = 0x00000000;
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s->afrl = 0x00000000;
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s->afrh = 0x00000000;
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s->ascr = 0x00000000;
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s->disconnected_pins = 0xFFFF;
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s->pins_connected_high = 0x0000;
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update_gpio_idr(s);
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}
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static void stm32l4x5_gpio_set(void *opaque, int line, int level)
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{
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Stm32l4x5GpioState *s = opaque;
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/*
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* The pin isn't set if line is configured in output mode
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* except if level is 0 and the output is open-drain.
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* This way there will be no short-circuit prone situations.
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*/
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if (is_output(s, line) && !(is_open_drain(s, line) && (level == 0))) {
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qemu_log_mask(LOG_GUEST_ERROR, "Line %d can't be driven externally\n",
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line);
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return;
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}
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s->disconnected_pins &= ~(1 << line);
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if (level) {
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s->pins_connected_high |= (1 << line);
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} else {
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s->pins_connected_high &= ~(1 << line);
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}
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trace_stm32l4x5_gpio_pins(s->name, s->disconnected_pins,
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s->pins_connected_high);
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update_gpio_idr(s);
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}
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static void update_gpio_idr(Stm32l4x5GpioState *s)
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{
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uint32_t new_idr_mask = 0;
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uint32_t new_idr = s->odr;
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uint32_t old_idr = s->idr;
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int new_pin_state, old_pin_state;
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for (int i = 0; i < GPIO_NUM_PINS; i++) {
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if (is_output(s, i)) {
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if (is_push_pull(s, i)) {
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new_idr_mask |= (1 << i);
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} else if (!(s->odr & (1 << i))) {
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/* open-drain ODR 0 */
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new_idr_mask |= (1 << i);
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/* open-drain ODR 1 */
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} else if (!(s->disconnected_pins & (1 << i)) &&
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!(s->pins_connected_high & (1 << i))) {
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/* open-drain ODR 1 with pin connected low */
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new_idr_mask |= (1 << i);
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new_idr &= ~(1 << i);
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/* open-drain ODR 1 with unactive pin */
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} else if (is_pull_up(s, i)) {
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new_idr_mask |= (1 << i);
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} else if (is_pull_down(s, i)) {
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new_idr_mask |= (1 << i);
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new_idr &= ~(1 << i);
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}
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/*
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* The only case left is for open-drain ODR 1
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* with unactive pin without pull-up or pull-down :
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* the value is floating.
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*/
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/* input or analog mode with connected pin */
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} else if (!(s->disconnected_pins & (1 << i))) {
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if (s->pins_connected_high & (1 << i)) {
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/* pin high */
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new_idr_mask |= (1 << i);
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new_idr |= (1 << i);
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} else {
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/* pin low */
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new_idr_mask |= (1 << i);
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new_idr &= ~(1 << i);
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}
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/* input or analog mode with disconnected pin */
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} else {
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if (is_pull_up(s, i)) {
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/* pull-up */
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new_idr_mask |= (1 << i);
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new_idr |= (1 << i);
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} else if (is_pull_down(s, i)) {
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/* pull-down */
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new_idr_mask |= (1 << i);
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new_idr &= ~(1 << i);
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}
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/*
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* The only case left is for a disconnected pin
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* without pull-up or pull-down :
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* the value is floating.
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*/
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}
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}
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s->idr = (old_idr & ~new_idr_mask) | (new_idr & new_idr_mask);
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trace_stm32l4x5_gpio_update_idr(s->name, old_idr, s->idr);
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for (int i = 0; i < GPIO_NUM_PINS; i++) {
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if (new_idr_mask & (1 << i)) {
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new_pin_state = (new_idr & (1 << i)) > 0;
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old_pin_state = (old_idr & (1 << i)) > 0;
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if (new_pin_state > old_pin_state) {
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qemu_irq_raise(s->pin[i]);
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} else if (new_pin_state < old_pin_state) {
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qemu_irq_lower(s->pin[i]);
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}
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}
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}
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}
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/*
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* Return mask of pins that are both configured in output
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* mode and externally driven (except pins in open-drain
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* mode externally set to 0).
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*/
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static uint32_t get_gpio_pinmask_to_disconnect(Stm32l4x5GpioState *s)
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{
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uint32_t pins_to_disconnect = 0;
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for (int i = 0; i < GPIO_NUM_PINS; i++) {
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/* for each connected pin in output mode */
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if (!(s->disconnected_pins & (1 << i)) && is_output(s, i)) {
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/* if either push-pull or high level */
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if (is_push_pull(s, i) || s->pins_connected_high & (1 << i)) {
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pins_to_disconnect |= (1 << i);
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qemu_log_mask(LOG_GUEST_ERROR,
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"Line %d can't be driven externally\n",
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i);
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}
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}
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}
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return pins_to_disconnect;
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}
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/*
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* Set field `disconnected_pins` and call `update_gpio_idr()`
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*/
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static void disconnect_gpio_pins(Stm32l4x5GpioState *s, uint16_t lines)
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{
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s->disconnected_pins |= lines;
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trace_stm32l4x5_gpio_pins(s->name, s->disconnected_pins,
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s->pins_connected_high);
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update_gpio_idr(s);
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}
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static void disconnected_pins_set(Object *obj, Visitor *v,
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const char *name, void *opaque, Error **errp)
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{
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Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
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uint16_t value;
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if (!visit_type_uint16(v, name, &value, errp)) {
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return;
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}
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disconnect_gpio_pins(s, value);
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}
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static void disconnected_pins_get(Object *obj, Visitor *v,
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const char *name, void *opaque, Error **errp)
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{
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visit_type_uint16(v, name, (uint16_t *)opaque, errp);
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}
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static void clock_freq_get(Object *obj, Visitor *v,
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const char *name, void *opaque, Error **errp)
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{
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Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
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uint32_t clock_freq_hz = clock_get_hz(s->clk);
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visit_type_uint32(v, name, &clock_freq_hz, errp);
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}
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static void stm32l4x5_gpio_write(void *opaque, hwaddr addr,
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uint64_t val64, unsigned int size)
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{
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Stm32l4x5GpioState *s = opaque;
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uint32_t value = val64;
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trace_stm32l4x5_gpio_write(s->name, addr, val64);
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switch (addr) {
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case GPIO_MODER:
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s->moder = value;
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disconnect_gpio_pins(s, get_gpio_pinmask_to_disconnect(s));
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qemu_log_mask(LOG_UNIMP,
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"%s: Analog and AF modes aren't supported\n\
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Analog and AF mode behave like input mode\n",
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__func__);
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return;
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case GPIO_OTYPER:
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s->otyper = value & ~RESERVED_BITS_MASK;
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disconnect_gpio_pins(s, get_gpio_pinmask_to_disconnect(s));
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return;
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case GPIO_OSPEEDR:
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qemu_log_mask(LOG_UNIMP,
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"%s: Changing I/O output speed isn't supported\n\
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I/O speed is already maximal\n",
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__func__);
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s->ospeedr = value;
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return;
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case GPIO_PUPDR:
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s->pupdr = value;
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update_gpio_idr(s);
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return;
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case GPIO_IDR:
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qemu_log_mask(LOG_UNIMP,
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"%s: GPIO->IDR is read-only\n",
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__func__);
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return;
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case GPIO_ODR:
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s->odr = value & ~RESERVED_BITS_MASK;
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update_gpio_idr(s);
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return;
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case GPIO_BSRR: {
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uint32_t bits_to_reset = (value & RESERVED_BITS_MASK) >> GPIO_NUM_PINS;
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uint32_t bits_to_set = value & ~RESERVED_BITS_MASK;
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/* If both BSx and BRx are set, BSx has priority.*/
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s->odr &= ~bits_to_reset;
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s->odr |= bits_to_set;
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update_gpio_idr(s);
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return;
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}
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case GPIO_LCKR:
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qemu_log_mask(LOG_UNIMP,
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"%s: Locking port bits configuration isn't supported\n",
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__func__);
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s->lckr = value & ~RESERVED_BITS_MASK;
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return;
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case GPIO_AFRL:
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qemu_log_mask(LOG_UNIMP,
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"%s: Alternate functions aren't supported\n",
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__func__);
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s->afrl = value;
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return;
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case GPIO_AFRH:
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qemu_log_mask(LOG_UNIMP,
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"%s: Alternate functions aren't supported\n",
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__func__);
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s->afrh = value;
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return;
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case GPIO_BRR: {
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uint32_t bits_to_reset = value & ~RESERVED_BITS_MASK;
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s->odr &= ~bits_to_reset;
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update_gpio_idr(s);
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return;
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}
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case GPIO_ASCR:
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qemu_log_mask(LOG_UNIMP,
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"%s: ADC function isn't supported\n",
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__func__);
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s->ascr = value & ~RESERVED_BITS_MASK;
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return;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
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}
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}
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static uint64_t stm32l4x5_gpio_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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Stm32l4x5GpioState *s = opaque;
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trace_stm32l4x5_gpio_read(s->name, addr);
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switch (addr) {
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case GPIO_MODER:
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return s->moder;
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case GPIO_OTYPER:
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return s->otyper;
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case GPIO_OSPEEDR:
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return s->ospeedr;
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case GPIO_PUPDR:
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return s->pupdr;
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case GPIO_IDR:
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return s->idr;
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case GPIO_ODR:
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return s->odr;
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case GPIO_BSRR:
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return 0;
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case GPIO_LCKR:
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return s->lckr;
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case GPIO_AFRL:
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return s->afrl;
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case GPIO_AFRH:
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return s->afrh;
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case GPIO_BRR:
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return 0;
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case GPIO_ASCR:
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return s->ascr;
|
||||
default:
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static const MemoryRegionOps stm32l4x5_gpio_ops = {
|
||||
.read = stm32l4x5_gpio_read,
|
||||
.write = stm32l4x5_gpio_write,
|
||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
||||
.impl = {
|
||||
.min_access_size = 4,
|
||||
.max_access_size = 4,
|
||||
.unaligned = false,
|
||||
},
|
||||
.valid = {
|
||||
.min_access_size = 4,
|
||||
.max_access_size = 4,
|
||||
.unaligned = false,
|
||||
},
|
||||
};
|
||||
|
||||
static void stm32l4x5_gpio_init(Object *obj)
|
||||
{
|
||||
Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
|
||||
|
||||
memory_region_init_io(&s->mmio, obj, &stm32l4x5_gpio_ops, s,
|
||||
TYPE_STM32L4X5_GPIO, 0x400);
|
||||
|
||||
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
|
||||
|
||||
qdev_init_gpio_out(DEVICE(obj), s->pin, GPIO_NUM_PINS);
|
||||
qdev_init_gpio_in(DEVICE(obj), stm32l4x5_gpio_set, GPIO_NUM_PINS);
|
||||
|
||||
s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0);
|
||||
|
||||
object_property_add(obj, "disconnected-pins", "uint16",
|
||||
disconnected_pins_get, disconnected_pins_set,
|
||||
NULL, &s->disconnected_pins);
|
||||
object_property_add(obj, "clock-freq-hz", "uint32",
|
||||
clock_freq_get, NULL, NULL, NULL);
|
||||
}
|
||||
|
||||
static void stm32l4x5_gpio_realize(DeviceState *dev, Error **errp)
|
||||
{
|
||||
Stm32l4x5GpioState *s = STM32L4X5_GPIO(dev);
|
||||
if (!clock_has_source(s->clk)) {
|
||||
error_setg(errp, "GPIO: clk input must be connected");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
static const VMStateDescription vmstate_stm32l4x5_gpio = {
|
||||
.name = TYPE_STM32L4X5_GPIO,
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.fields = (VMStateField[]){
|
||||
VMSTATE_UINT32(moder, Stm32l4x5GpioState),
|
||||
VMSTATE_UINT32(otyper, Stm32l4x5GpioState),
|
||||
VMSTATE_UINT32(ospeedr, Stm32l4x5GpioState),
|
||||
VMSTATE_UINT32(pupdr, Stm32l4x5GpioState),
|
||||
VMSTATE_UINT32(idr, Stm32l4x5GpioState),
|
||||
VMSTATE_UINT32(odr, Stm32l4x5GpioState),
|
||||
VMSTATE_UINT32(lckr, Stm32l4x5GpioState),
|
||||
VMSTATE_UINT32(afrl, Stm32l4x5GpioState),
|
||||
VMSTATE_UINT32(afrh, Stm32l4x5GpioState),
|
||||
VMSTATE_UINT32(ascr, Stm32l4x5GpioState),
|
||||
VMSTATE_UINT16(disconnected_pins, Stm32l4x5GpioState),
|
||||
VMSTATE_UINT16(pins_connected_high, Stm32l4x5GpioState),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
static Property stm32l4x5_gpio_properties[] = {
|
||||
DEFINE_PROP_STRING("name", Stm32l4x5GpioState, name),
|
||||
DEFINE_PROP_UINT32("mode-reset", Stm32l4x5GpioState, moder_reset, 0),
|
||||
DEFINE_PROP_UINT32("ospeed-reset", Stm32l4x5GpioState, ospeedr_reset, 0),
|
||||
DEFINE_PROP_UINT32("pupd-reset", Stm32l4x5GpioState, pupdr_reset, 0),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static void stm32l4x5_gpio_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
ResettableClass *rc = RESETTABLE_CLASS(klass);
|
||||
|
||||
device_class_set_props(dc, stm32l4x5_gpio_properties);
|
||||
dc->vmsd = &vmstate_stm32l4x5_gpio;
|
||||
dc->realize = stm32l4x5_gpio_realize;
|
||||
rc->phases.hold = stm32l4x5_gpio_reset_hold;
|
||||
}
|
||||
|
||||
static const TypeInfo stm32l4x5_gpio_types[] = {
|
||||
{
|
||||
.name = TYPE_STM32L4X5_GPIO,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(Stm32l4x5GpioState),
|
||||
.instance_init = stm32l4x5_gpio_init,
|
||||
.class_init = stm32l4x5_gpio_class_init,
|
||||
},
|
||||
};
|
||||
|
||||
DEFINE_TYPES(stm32l4x5_gpio_types)
|
||||
@ -31,3 +31,9 @@ sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " val
|
||||
# aspeed_gpio.c
|
||||
aspeed_gpio_read(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64
|
||||
aspeed_gpio_write(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64
|
||||
|
||||
# stm32l4x5_gpio.c
|
||||
stm32l4x5_gpio_read(char *gpio, uint64_t addr) "GPIO%s addr: 0x%" PRIx64 " "
|
||||
stm32l4x5_gpio_write(char *gpio, uint64_t addr, uint64_t data) "GPIO%s addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
|
||||
stm32l4x5_gpio_update_idr(char *gpio, uint32_t old_idr, uint32_t new_idr) "GPIO%s from: 0x%x to: 0x%x"
|
||||
stm32l4x5_gpio_pins(char *gpio, uint16_t disconnected, uint16_t high) "GPIO%s disconnected pins: 0x%x levels: 0x%x"
|
||||
|
||||
70
include/hw/gpio/stm32l4x5_gpio.h
Normal file
70
include/hw/gpio/stm32l4x5_gpio.h
Normal file
@ -0,0 +1,70 @@
|
||||
/*
|
||||
* STM32L4x5 GPIO (General Purpose Input/Ouput)
|
||||
*
|
||||
* Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
|
||||
* Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*
|
||||
* This work is licensed under the terms of the GNU GPL, version 2 or later.
|
||||
* See the COPYING file in the top-level directory.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The reference used is the STMicroElectronics RM0351 Reference manual
|
||||
* for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
|
||||
* https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
|
||||
*/
|
||||
|
||||
#ifndef HW_STM32L4X5_GPIO_H
|
||||
#define HW_STM32L4X5_GPIO_H
|
||||
|
||||
#include "hw/sysbus.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5GpioState, STM32L4X5_GPIO)
|
||||
|
||||
#define GPIO_NUM_PINS 16
|
||||
|
||||
struct Stm32l4x5GpioState {
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
MemoryRegion mmio;
|
||||
|
||||
/* GPIO registers */
|
||||
uint32_t moder;
|
||||
uint32_t otyper;
|
||||
uint32_t ospeedr;
|
||||
uint32_t pupdr;
|
||||
uint32_t idr;
|
||||
uint32_t odr;
|
||||
uint32_t lckr;
|
||||
uint32_t afrl;
|
||||
uint32_t afrh;
|
||||
uint32_t ascr;
|
||||
|
||||
/* GPIO registers reset values */
|
||||
uint32_t moder_reset;
|
||||
uint32_t ospeedr_reset;
|
||||
uint32_t pupdr_reset;
|
||||
|
||||
/*
|
||||
* External driving of pins.
|
||||
* The pins can be set externally through the device
|
||||
* anonymous input GPIOs lines under certain conditions.
|
||||
* The pin must not be in push-pull output mode,
|
||||
* and can't be set high in open-drain mode.
|
||||
* Pins driven externally and configured to
|
||||
* output mode will in general be "disconnected"
|
||||
* (see `get_gpio_pinmask_to_disconnect()`)
|
||||
*/
|
||||
uint16_t disconnected_pins;
|
||||
uint16_t pins_connected_high;
|
||||
|
||||
char *name;
|
||||
Clock *clk;
|
||||
qemu_irq pin[GPIO_NUM_PINS];
|
||||
};
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user