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target/arm: Convert T16 add pc/sp (immediate)

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-50-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2019-09-04 12:30:39 -07:00 committed by Peter Maydell
parent 07afd747f9
commit 1cb1323433
2 changed files with 8 additions and 11 deletions
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7
target/arm/t16.decode
View File

@ -23,6 +23,7 @@
&s_rrr_shr !extern s rn rd rm rs shty &s_rrr_shr !extern s rn rd rm rs shty
&s_rri_rot !extern s rn rd imm rot &s_rri_rot !extern s rn rd imm rot
&s_rrrr !extern s rd rn rm ra &s_rrrr !extern s rd rn rm ra
&ri !extern rd imm
&ldst_rr !extern p w u rn rt rm shimm shtype &ldst_rr !extern p w u rn rt rm shimm shtype
&ldst_ri !extern p w u rn rt imm &ldst_ri !extern p w u rn rt imm
@ -102,3 +103,9 @@ LDRH_ri 10001 ..... ... ... @ldst_ri_2
STR_ri 10010 ... ........ @ldst_spec_i rn=13 STR_ri 10010 ... ........ @ldst_spec_i rn=13
LDR_ri 10011 ... ........ @ldst_spec_i rn=13 LDR_ri 10011 ... ........ @ldst_spec_i rn=13
# Add PC/SP (immediate)
ADR 10100 rd:3 ........ imm=%imm8_0x4
ADD_rri 10101 rd:3 ........ \
&s_rri_rot rn=13 s=0 rot=0 imm=%imm8_0x4 # SP

12
target/arm/translate.c
View File

@ -10868,19 +10868,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
case 7: /* load/store byte immediate offset, in decodetree */ case 7: /* load/store byte immediate offset, in decodetree */
case 8: /* load/store halfword immediate offset, in decodetree */ case 8: /* load/store halfword immediate offset, in decodetree */
case 9: /* load/store from stack, in decodetree */ case 9: /* load/store from stack, in decodetree */
case 10: /* add PC/SP (immediate), in decodetree */
goto illegal_op; goto illegal_op;
case 10:
/*
* 0b1010_xxxx_xxxx_xxxx
* - Add PC/SP (immediate)
*/
rd = (insn >> 8) & 7;
val = (insn & 0xff) * 4;
tmp = add_reg_for_lit(s, insn & (1 << 11) ? 13 : 15, val);
store_reg(s, rd, tmp);
break;
case 11: case 11:
/* misc */ /* misc */
op = (insn >> 8) & 0xf; op = (insn >> 8) & 0xf;