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target/arm: Split out formats for 2 vectors + 1 index

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Currently only used by FMUL, but will shortly be used more.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-52-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2021-05-24 18:03:17 -07:00 committed by Peter Maydell
parent 636ddeb15c
commit 1c737d9c5f
1 changed files with 10 additions and 4 deletions
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14
target/arm/sve.decode
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@ -67,6 +67,7 @@
&rri_esz rd rn imm esz
&rrri_esz rd rn rm imm esz
&rrr_esz rd rn rm esz
&rrx_esz rd rn rm index esz
&rpr_esz rd pg rn esz
&rpr_s rd pg rn s
&rprr_s rd pg rn rm s
@ -245,6 +246,12 @@
@rpri_scatter_store ....... msz:2 .. imm:5 ... pg:3 rn:5 rd:5 \
&rpri_scatter_store
# Two registers and a scalar by N-bit index
@rrx_3 ........ .. . .. rm:3 ...... rn:5 rd:5 \
&rrx_esz index=%index3_22_19
@rrx_2 ........ .. . index:2 rm:3 ...... rn:5 rd:5 &rrx_esz
@rrx_1 ........ .. . index:1 rm:4 ...... rn:5 rd:5 &rrx_esz
###########################################################################
# Instruction patterns. Grouped according to the SVE encodingindex.xhtml.
@ -792,10 +799,9 @@ FMLA_zzxz 01100100 111 index:1 rm:4 00000 sub:1 rn:5 rd:5 \
### SVE FP Multiply Indexed Group
# SVE floating-point multiply (indexed)
FMUL_zzx 01100100 0.1 .. rm:3 001000 rn:5 rd:5 \
index=%index3_22_19 esz=1
FMUL_zzx 01100100 101 index:2 rm:3 001000 rn:5 rd:5 esz=2
FMUL_zzx 01100100 111 index:1 rm:4 001000 rn:5 rd:5 esz=3
FMUL_zzx 01100100 0. 1 ..... 001000 ..... ..... @rrx_3 esz=1
FMUL_zzx 01100100 10 1 ..... 001000 ..... ..... @rrx_2 esz=2
FMUL_zzx 01100100 11 1 ..... 001000 ..... ..... @rrx_1 esz=3
### SVE FP Fast Reduction Group