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tcg: Add type for vCPU pointers

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Adds the 'TCGv_env' type for pointers to 'CPUArchState' objects. The
tracing infrastructure later needs to differentiate between regular
pointers and pointers to vCPUs.

Also changes all targets to use the new 'TCGv_env' type instead of the
generic 'TCGv_ptr'. As of now, the change is merely cosmetic ('TCGv_env'
translates into 'TCGv_ptr'), but that could change in the future to
enforce the difference.

Note that a 'TCGv_env' type (for 'CPUState') is not added, since all
helpers currently receive the architecture-specific
pointer ('CPUArchState').

Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Acked-by: Richard Henderson <rth@twiddle.net>
Message-id: 145641859552.30295.7821536833590725201.stgit@localhost
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Lluís Vilanova 2016-02-25 17:43:15 +01:00 committed by Stefan Hajnoczi
parent 56797b1fbc
commit 1bcea73e13
20 changed files with 22 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
target-alpha/translate.c
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@ -93,7 +93,7 @@ typedef enum {
} ExitStatus;
/* global register indexes */
static TCGv_ptr cpu_env;
static TCGv_env cpu_env;
static TCGv cpu_std_ir[31];
static TCGv cpu_fir[31];
static TCGv cpu_pc;

2
target-arm/translate.c
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@ -56,7 +56,7 @@
#define IS_USER(s) (s->user)
#endif
TCGv_ptr cpu_env;
TCGv_env cpu_env;
/* We reuse the same 64-bit temporaries for efficiency. */
static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
static TCGv_i32 cpu_R[16];

2
target-arm/translate.h
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@ -70,7 +70,7 @@ typedef struct DisasCompare {
} DisasCompare;
/* Share the TCG temporaries common between 32 and 64 bit modes. */
extern TCGv_ptr cpu_env;
extern TCGv_env cpu_env;
extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
extern TCGv_i64 cpu_exclusive_addr;
extern TCGv_i64 cpu_exclusive_val;

2
target-cris/translate.c
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@ -60,7 +60,7 @@
#define CC_MASK_NZVC 0xf
#define CC_MASK_RNZV 0x10e
static TCGv_ptr cpu_env;
static TCGv_env cpu_env;
static TCGv cpu_R[16];
static TCGv cpu_PR[16];
static TCGv cc_x;

2
target-i386/translate.c
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@ -65,7 +65,7 @@
//#define MACRO_TEST 1
/* global register indexes */
static TCGv_ptr cpu_env;
static TCGv_env cpu_env;
static TCGv cpu_A0;
static TCGv cpu_cc_dst, cpu_cc_src, cpu_cc_src2, cpu_cc_srcT;
static TCGv_i32 cpu_cc_op;

2
target-lm32/translate.c
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@ -44,7 +44,7 @@
#define MEM_INDEX 0
static TCGv_ptr cpu_env;
static TCGv_env cpu_env;
static TCGv cpu_R[32];
static TCGv cpu_pc;
static TCGv cpu_ie;

2
target-m68k/translate.c
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@ -50,7 +50,7 @@
static TCGv_i32 cpu_halted;
static TCGv_i32 cpu_exception_index;
static TCGv_ptr cpu_env;
static TCGv_env cpu_env;
static char cpu_reg_names[3*8*3 + 5*4];
static TCGv cpu_dregs[8];

2
target-microblaze/translate.c
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@ -46,7 +46,7 @@
(((src) >> start) & ((1 << (end - start + 1)) - 1))
static TCGv env_debug;
static TCGv_ptr cpu_env;
static TCGv_env cpu_env;
static TCGv cpu_R[32];
static TCGv cpu_SR[18];
static TCGv env_imm;

2
target-mips/translate.c
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@ -1355,7 +1355,7 @@ enum {
};
/* global register indices */
static TCGv_ptr cpu_env;
static TCGv_env cpu_env;
static TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
static TCGv cpu_dspctrl, btarget, bcond;

2
target-moxie/translate.c
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@ -56,7 +56,7 @@ enum {
static TCGv cpu_pc;
static TCGv cpu_gregs[16];
static TCGv_ptr cpu_env;
static TCGv_env cpu_env;
static TCGv cc_a, cc_b;
#include "exec/gen-icount.h"

2
target-openrisc/translate.c
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@ -53,7 +53,7 @@ typedef struct DisasContext {
uint32_t delayed_branch;
} DisasContext;
static TCGv_ptr cpu_env;
static TCGv_env cpu_env;
static TCGv cpu_sr;
static TCGv cpu_R[32];
static TCGv cpu_pc;

2
target-ppc/translate.c
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@ -49,7 +49,7 @@
/* Code translation helpers */
/* global register indexes */
static TCGv_ptr cpu_env;
static TCGv_env cpu_env;
static char cpu_reg_names[10*3 + 22*4 /* GPR */
+ 10*4 + 22*5 /* SPE GPRh */
+ 10*4 + 22*5 /* FPR */

2
target-s390x/translate.c
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@ -37,7 +37,7 @@
#include "exec/cpu_ldst.h"
/* global register indexes */
static TCGv_ptr cpu_env;
static TCGv_env cpu_env;
#include "exec/gen-icount.h"
#include "exec/helper-proto.h"

2
target-sh4/translate.c
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@ -61,7 +61,7 @@ enum {
};
/* global register indexes */
static TCGv_ptr cpu_env;
static TCGv_env cpu_env;
static TCGv cpu_gregs[24];
static TCGv cpu_sr, cpu_sr_m, cpu_sr_q, cpu_sr_t;
static TCGv cpu_pc, cpu_ssr, cpu_spc, cpu_gbr;

5
target-sparc/translate.c
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@ -39,7 +39,8 @@
according to jump_pc[T2] */
/* global register indexes */
static TCGv_ptr cpu_env, cpu_regwptr;
static TCGv_env cpu_env;
static TCGv_ptr cpu_regwptr;
static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
static TCGv_i32 cpu_cc_op;
static TCGv_i32 cpu_psr;
@ -2291,7 +2292,7 @@ static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
}
#ifndef CONFIG_USER_ONLY
static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_ptr cpu_env)
static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env cpu_env)
{
TCGv_i32 r_tl = tcg_temp_new_i32();

2
target-tilegx/translate.c
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@ -32,7 +32,7 @@
#define FMT64X "%016" PRIx64
static TCGv_ptr cpu_env;
static TCGv_env cpu_env;
static TCGv cpu_pc;
static TCGv cpu_regs[TILEGX_R_COUNT];

2
target-tricore/translate.c
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@ -47,7 +47,7 @@ static TCGv cpu_PSW_SV;
static TCGv cpu_PSW_AV;
static TCGv cpu_PSW_SAV;
/* CPU env */
static TCGv_ptr cpu_env;
static TCGv_env cpu_env;
#include "exec/gen-icount.h"

2
target-unicore32/translate.c
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@ -48,7 +48,7 @@ typedef struct DisasContext {
conditional executions state has been updated. */
#define DISAS_SYSCALL 5
static TCGv_ptr cpu_env;
static TCGv_env cpu_env;
static TCGv_i32 cpu_R[32];
/* FIXME: These should be removed. */

2
target-xtensa/translate.c
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@ -74,7 +74,7 @@ typedef struct DisasContext {
unsigned cpenable;
} DisasContext;
static TCGv_ptr cpu_env;
static TCGv_env cpu_env;
static TCGv_i32 cpu_pc;
static TCGv_i32 cpu_R[16];
static TCGv_i32 cpu_FR[16];

1
tcg/tcg.h
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@ -308,6 +308,7 @@ typedef tcg_target_ulong TCGArg;
typedef struct TCGv_i32_d *TCGv_i32;
typedef struct TCGv_i64_d *TCGv_i64;
typedef struct TCGv_ptr_d *TCGv_ptr;
typedef TCGv_ptr TCGv_env;
static inline TCGv_i32 QEMU_ARTIFICIAL MAKE_TCGV_I32(intptr_t i)
{