target-arm: Don't use cpu_single_env in bank_number()
Avoid using cpu_single_env in bank_number() -- if we were called via the gdb stub reading or writing the CPSR then it is NULL and we will segfault if we take the cpu_abort(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -642,7 +642,7 @@ uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
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extern int semihosting_enabled;
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/* Map CPU modes onto saved register banks. */
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static inline int bank_number (int mode)
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static inline int bank_number(CPUState *env, int mode)
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{
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switch (mode) {
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case ARM_CPU_MODE_USR:
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@ -659,7 +659,7 @@ static inline int bank_number (int mode)
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case ARM_CPU_MODE_FIQ:
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return 5;
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}
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cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
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cpu_abort(env, "Bad mode %x\n", mode);
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return -1;
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}
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@ -680,12 +680,12 @@ void switch_mode(CPUState *env, int mode)
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memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
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}
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i = bank_number(old_mode);
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i = bank_number(env, old_mode);
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env->banked_r13[i] = env->regs[13];
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env->banked_r14[i] = env->regs[14];
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env->banked_spsr[i] = env->spsr;
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i = bank_number(mode);
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i = bank_number(env, mode);
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env->regs[13] = env->banked_r13[i];
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env->regs[14] = env->banked_r14[i];
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env->spsr = env->banked_spsr[i];
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@ -2125,7 +2125,7 @@ void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
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if ((env->uncached_cpsr & CPSR_M) == mode) {
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env->regs[13] = val;
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} else {
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env->banked_r13[bank_number(mode)] = val;
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env->banked_r13[bank_number(env, mode)] = val;
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}
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}
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@ -2134,7 +2134,7 @@ uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
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if ((env->uncached_cpsr & CPSR_M) == mode) {
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return env->regs[13];
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} else {
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return env->banked_r13[bank_number(mode)];
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return env->banked_r13[bank_number(env, mode)];
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}
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}
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