From 1b5e843ab68c4afa611da22f303a5b0daa979ad8 Mon Sep 17 00:00:00 2001 From: Igor Mammedov Date: Tue, 6 Oct 2020 11:00:02 -0400 Subject: [PATCH] numa: hmat: require parent cache description before the next level one Spec[1] defines 0 - 3 level memory side cache, however QEMU CLI allows to specify an intermediate cache level without specifying previous level. Such option(s) silently ignored when building HMAT table, which leads to incomplete cache information. Make sure that previous level exists and error out if it hasn't been provided. 1) ACPI 6.2A 5.2.27.5 Memory Side Cache Information Structure Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1842877 Signed-off-by: Igor Mammedov Signed-off-by: Eduardo Habkost Message-Id: <20201006150002.1601845-1-imammedo@redhat.com> Signed-off-by: Eduardo Habkost --- hw/core/numa.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/core/numa.c b/hw/core/numa.c index 7d5d413001..7c4dd4e68e 100644 --- a/hw/core/numa.c +++ b/hw/core/numa.c @@ -424,7 +424,13 @@ void parse_numa_hmat_cache(MachineState *ms, NumaHmatCacheOptions *node, } if ((node->level > 1) && - ms->numa_state->hmat_cache[node->node_id][node->level - 1] && + ms->numa_state->hmat_cache[node->node_id][node->level - 1] == NULL) { + error_setg(errp, "Cache level=%u shall be defined first", + node->level - 1); + return; + } + + if ((node->level > 1) && (node->size <= ms->numa_state->hmat_cache[node->node_id][node->level - 1]->size)) { error_setg(errp, "Invalid size=%" PRIu64 ", the size of level=%" PRIu8