X86 queue, 2015-07-07
Patch "target-i386: emulate CPUID level of real hardware" was removed after the 2015-07-03 pull request. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJVm+Y/AAoJECgHk2+YTcWm384P/2ARe6Svz3/y6U/c0ZyPxNWw Rptm3DPCqBGg/Hvmu6LHXsUUrHP7i+N+QtrQ/y0ybTVjTt3bUJoCVTYo9nUnV7+X 1TPrPMzsB+TSJo7Thk5LWzEIwr9bxlZpFEl7I3lyKuxsaV44knHLUYuMx7A82D44 QREn6T8V2k0jp2eEPedkddp3WyVGQiRN/Uy+wPxHXvnxEQyMo8sU3XWh7OolSrx0 qCslbfK4FtRxtYxeXtGO4h87YXhVCtxuAGgdoE7sJpSpakwjx5n1eXQSdlq306ax ncSPRPl+r7lbexYWkhzxWjw6IvJk5r+ZHPSBy9NHdAgWG9dCyW+Gx5WSobCrGWbn KfBbnd13ZnLdaTtpYsCBaJcWr2PQDwpyQsEyOMInqZVv0r/7gL2Sl4OSBKgXNmme tsVWNEHWKFYpi34wNwR3bgKwbu+pjlrWylhYaa6v35V6/PoK70yvRtJEYlcb7z8D xUPGXc2SWDkAlBqFRVwl+6MO7bPZ6xKkwjOX/iON7dlNNxV49xsYPfuY2lZ1pxNZ wlcM5J2a9ECbG9n8bBdNp7v1zy3mgY4wq1cQi8yGfLhhGfievIVIMkif/jbAwT5p 2KXBfgXhZ3UQBkpJUzXBhpCzYrM5OiPjiYi/yb15khloW1ayXApSCOwbGb1OW1QL hoDXnEGv1c5nqkD20keX =v+Bn -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging X86 queue, 2015-07-07 Patch "target-i386: emulate CPUID level of real hardware" was removed after the 2015-07-03 pull request. # gpg: Signature made Tue Jul 7 15:46:23 2015 BST using RSA key ID 984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-pull-request: target-i386: avoid overflow in the tsc-frequency property i386: Introduce ARAT CPU feature Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
1a632032d1
@ -293,7 +293,12 @@ int e820_get_num_entries(void);
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bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
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#define PC_COMPAT_2_3 \
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HW_COMPAT_2_3
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HW_COMPAT_2_3 \
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{\
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.driver = TYPE_X86_CPU,\
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.property = "arat",\
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.value = "off",\
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},
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#define PC_COMPAT_2_2 \
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PC_COMPAT_2_3 \
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@ -286,6 +286,17 @@ static const char *cpuid_xsave_feature_name[] = {
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NULL, NULL, NULL, NULL,
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};
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static const char *cpuid_6_feature_name[] = {
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NULL, NULL, "arat", NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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};
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#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
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#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
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CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
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@ -341,6 +352,7 @@ static const char *cpuid_xsave_feature_name[] = {
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CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
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CPUID_7_0_EBX_RDSEED */
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#define TCG_APM_FEATURES 0
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#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
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typedef struct FeatureWordInfo {
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@ -410,6 +422,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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.cpuid_reg = R_EAX,
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.tcg_features = 0,
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},
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[FEAT_6_EAX] = {
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.feat_names = cpuid_6_feature_name,
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.cpuid_eax = 6, .cpuid_reg = R_EAX,
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.tcg_features = TCG_6_EAX_FEATURES,
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},
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};
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typedef struct X86RegisterInfo32 {
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@ -1003,6 +1020,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
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.features[FEAT_8000_0001_ECX] =
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CPUID_EXT3_LAHF_LM,
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.features[FEAT_6_EAX] =
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CPUID_6_EAX_ARAT,
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.xlevel = 0x8000000A,
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.model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
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},
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@ -1032,6 +1051,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_EXT3_LAHF_LM,
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.features[FEAT_XSAVE] =
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CPUID_XSAVE_XSAVEOPT,
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.features[FEAT_6_EAX] =
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CPUID_6_EAX_ARAT,
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.xlevel = 0x8000000A,
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.model_id = "Intel Xeon E312xx (Sandy Bridge)",
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},
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@ -1064,6 +1085,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_EXT3_LAHF_LM,
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.features[FEAT_XSAVE] =
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CPUID_XSAVE_XSAVEOPT,
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.features[FEAT_6_EAX] =
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CPUID_6_EAX_ARAT,
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.xlevel = 0x8000000A,
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.model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
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},
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@ -1098,6 +1121,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
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.features[FEAT_XSAVE] =
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CPUID_XSAVE_XSAVEOPT,
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.features[FEAT_6_EAX] =
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CPUID_6_EAX_ARAT,
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.xlevel = 0x8000000A,
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.model_id = "Intel Core Processor (Haswell, no TSX)",
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}, {
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@ -1132,6 +1157,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_7_0_EBX_RTM,
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.features[FEAT_XSAVE] =
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CPUID_XSAVE_XSAVEOPT,
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.features[FEAT_6_EAX] =
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CPUID_6_EAX_ARAT,
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.xlevel = 0x8000000A,
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.model_id = "Intel Core Processor (Haswell)",
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},
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@ -1168,6 +1195,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_7_0_EBX_SMAP,
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.features[FEAT_XSAVE] =
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CPUID_XSAVE_XSAVEOPT,
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.features[FEAT_6_EAX] =
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CPUID_6_EAX_ARAT,
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.xlevel = 0x8000000A,
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.model_id = "Intel Core Processor (Broadwell, no TSX)",
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},
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@ -1204,6 +1233,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_7_0_EBX_SMAP,
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.features[FEAT_XSAVE] =
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CPUID_XSAVE_XSAVEOPT,
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.features[FEAT_6_EAX] =
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CPUID_6_EAX_ARAT,
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.xlevel = 0x8000000A,
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.model_id = "Intel Core Processor (Broadwell)",
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},
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@ -2359,7 +2390,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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break;
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case 6:
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/* Thermal and Power Leaf */
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*eax = 0;
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*eax = env->features[FEAT_6_EAX];
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*ebx = 0;
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*ecx = 0;
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*edx = 0;
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@ -415,6 +415,7 @@ typedef enum FeatureWord {
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FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
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FEAT_SVM, /* CPUID[8000_000A].EDX */
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FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */
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FEAT_6_EAX, /* CPUID[6].EAX */
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FEATURE_WORDS,
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} FeatureWord;
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@ -580,6 +581,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
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#define CPUID_XSAVE_XGETBV1 (1U << 2)
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#define CPUID_XSAVE_XSAVES (1U << 3)
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#define CPUID_6_EAX_ARAT (1U << 2)
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/* CPUID[0x80000007].EDX flags: */
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#define CPUID_APM_INVTSC (1U << 8)
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@ -959,7 +962,7 @@ typedef struct CPUX86State {
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uint8_t has_error_code;
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uint32_t sipi_vector;
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bool tsc_valid;
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int tsc_khz;
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int64_t tsc_khz;
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void *kvm_xsave_buf;
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uint64_t mcg_cap;
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@ -238,6 +238,8 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
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if (!kvm_irqchip_in_kernel()) {
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ret &= ~CPUID_EXT_X2APIC;
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}
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} else if (function == 6 && reg == R_EAX) {
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ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
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} else if (function == 0x80000001 && reg == R_EDX) {
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/* On Intel, kvm returns cpuid according to the Intel spec,
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* so add missing bits according to the AMD spec:
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