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target-mips: Fix incorrect shift for SHILO and SHILOV

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helper_shilo has not been shifting an accumulator value correctly for negative
values in 'shift' field. Minor optimization for shift=0 case.
This change also adds tests that will trigger issue and check for regressions.

Signed-off-by: Petar Jovanovic <petarj@mips.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Eric Johnson <ericj@mips.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Petar Jovanovic 2012-12-05 00:29:10 +01:00 committed by Aurelien Jarno
parent 34f5606ee1
commit 19e6c50d2d
3 changed files with 47 additions and 8 deletions
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17
target-mips/dsp_helper.c
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@ -3814,17 +3814,18 @@ void helper_shilo(target_ulong ac, target_ulong rs, CPUMIPSState *env)
rs5_0 = rs & 0x3F; rs5_0 = rs & 0x3F;
rs5_0 = (int8_t)(rs5_0 << 2) >> 2; rs5_0 = (int8_t)(rs5_0 << 2) >> 2;
rs5_0 = MIPSDSP_ABS(rs5_0);
if (unlikely(rs5_0 == 0)) {
return;
}
acc = (((uint64_t)env->active_tc.HI[ac] << 32) & MIPSDSP_LHI) | acc = (((uint64_t)env->active_tc.HI[ac] << 32) & MIPSDSP_LHI) |
((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
if (rs5_0 == 0) {
temp = acc; if (rs5_0 > 0) {
temp = acc >> rs5_0;
} else { } else {
if (rs5_0 > 0) { temp = acc << -rs5_0;
temp = acc >> rs5_0;
} else {
temp = acc << rs5_0;
}
} }
env->active_tc.HI[ac] = (target_ulong)(int32_t)((temp & MIPSDSP_LHI) >> 32); env->active_tc.HI[ac] = (target_ulong)(int32_t)((temp & MIPSDSP_LHI) >> 32);

18
tests/tcg/mips/mips32-dsp/shilo.c
View File

@ -23,5 +23,23 @@ int main()
assert(ach == resulth); assert(ach == resulth);
assert(acl == resultl); assert(acl == resultl);
ach = 0x1;
acl = 0x80000000;
resulth = 0x3;
resultl = 0x0;
__asm
("mthi %0, $ac1\n\t"
"mtlo %1, $ac1\n\t"
"shilo $ac1, -1\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
: "+r"(ach), "+r"(acl)
);
assert(ach == resulth);
assert(acl == resultl);
return 0; return 0;
} }

20
tests/tcg/mips/mips32-dsp/shilov.c
View File

@ -25,5 +25,25 @@ int main()
assert(ach == resulth); assert(ach == resulth);
assert(acl == resultl); assert(acl == resultl);
rs = 0xffffffff;
ach = 0x1;
acl = 0x80000000;
resulth = 0x3;
resultl = 0x0;
__asm
("mthi %0, $ac1\n\t"
"mtlo %1, $ac1\n\t"
"shilov $ac1, %2\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
: "+r"(ach), "+r"(acl)
: "r"(rs)
);
assert(ach == resulth);
assert(acl == resultl);
return 0; return 0;
} }